Integrated circuit memory having a fuse detect circuit and method therefor
First Claim
1. A fuse detect circuit, comprising:
- a fuse state detect stage for providing an output signal of a first logic state in response to detecting a fuse is an open circuit, and for providing the output signal of a second logic state in response to detecting the fuse is a short circuit, wherein the fuse state detect stage limits a voltage drop across the fuse to an absolute value independent of a power supply voltage value applied to the fuse detect circuit; and
a latch stage, coupled to the fuse state detect stage, for latching a logic state of the output signal.
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Accused Products
Abstract
Fuses and detect circuits (124) in an integrated circuit memory (100) include a copper fuse (208) and a fuse state detect stage (202) for detecting the open circuit state or the closed circuit state of the fuse (208). The fuse detect circuit (124) provides an output signal corresponding to the state of the fuse and during detecting, limits a voltage drop across the fuse to an absolute value independent of a power supply voltage applied to the integrated circuit memory. The fuse detect circuit (124) operates at power up of the integrated circuit memory (100) and is disabled after the state of the fuse is detected and latched, and the power supply is sufficient for reliable operation of the integrated circuit memory (100). By limiting the voltage drop across a blown copper fuse (208), a potential electro-migration problem is reduced.
67 Citations
20 Claims
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1. A fuse detect circuit, comprising:
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a fuse state detect stage for providing an output signal of a first logic state in response to detecting a fuse is an open circuit, and for providing the output signal of a second logic state in response to detecting the fuse is a short circuit, wherein the fuse state detect stage limits a voltage drop across the fuse to an absolute value independent of a power supply voltage value applied to the fuse detect circuit; and a latch stage, coupled to the fuse state detect stage, for latching a logic state of the output signal. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. An integrated circuit memory, comprising:
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a plurality of memory cells; a plurality of redundant memory cells; address decoding circuits, coupled to the plurality of memory cells and to the plurality of redundant memory cells, for selecting a memory cell in response to receiving an address; and a plurality of fuse detect circuits, coupled to the plurality of memory cells and to the plurality of redundant memory cells, for identifying a defective memory cell, and for identifying which of the plurality of redundant memory cells replaces the defective memory cell, a fuse detect circuit of the plurality of fuse detect circuits comprising; a fuse having an open circuit state and a short circuit state; and a circuit for detecting the open circuit state or the short circuit state of the fuse, and for providing a corresponding output signal, wherein during the detecting, the circuit limits a voltage drop across the fuse to an absolute value independent of a power supply voltage value applied to the integrated circuit memory. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17, 18)
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19. In an integrated circuit memory, a method for implementing a fuse comprising the steps of:
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providing a fuse comprising copper, wherein the fuse, if intact, provides a first logic state and the fuse, if blown, provides a second logic state; detecting if the fuse is blown or intact using a fuse detect circuit; limiting a voltage drop across the fuse when the fuse is blown to an absolute value independent of a power supply voltage applied to the integrated circuit memory; storing a logic state of the fuse; and disabling the fuse detect circuit in response to the power supply voltage being sufficient for reliable operation of the integrated circuit memory. - View Dependent Claims (20)
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Specification