Apparatus and method for selectively outputting data using a MAC layer interface or a PCI bus interface

• US 6,157,623 A
• Filed: 12/18/1997
• Issued: 12/05/2000
• Est. Priority Date: 02/14/1997
• Status: Expired due to Term

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Kerstein, Denise
• Primary Examiner(s): Pham, Chi H.
• Assistant Examiner(s): Pham, Brenda H.
• Application Number:
  US08/992,424
• Time in Patent Office: 1,083 Days
• Field of Search: 370/231, 370/232, 370/233, 370/234, 370/235, 370/236, 370/229, 370/230, 370/413, 370/359, 370/364, 370/419, 370/315
• US Class Current: 370/315
• CPC Class Codes: G06F 13/1605 based on arbitration arbitration in handling access to a common bus or bus system G06F13/36
• CPC Class Codes: G06F 13/24 using interrupt G06F13/32 takes precedence
• CPC Class Codes: G11C 11/412 using field-effect transistors only
• CPC Class Codes: H04L 12/1863 comprising mechanisms for improved reliability, e.g. status reports arrangements for detecting or preventing errors by carrying supervisory signal the return channel H04L1/16
• CPC Class Codes: H04L 12/4641 Virtual LANs, VLANs, e.g. virtual private networks [VPN] LAN interconnection over a bridge based backbone H04L12/462; encapsulation techniques H04L12/4633; routing of packets H04L45/00; packet switches H04L49/00; virtual private networks for security H04L63/0272
• CPC Class Codes: H04L 12/4645 Details on frame tagging routing of packets H04L45/00; support for virtual LAN H04L49/354
• CPC Class Codes: H04L 12/467 Arrangements for supporting untagged frames, e.g. port-based VLANs
• CPC Class Codes: H04L 41/0213 Standardised network management protocols, e.g. simple network management protocol [SNMP]
• CPC Class Codes: H04L 47/50 Queue scheduling
• CPC Class Codes: H04L 47/6225 Fixed service order, e.g. Round Robin
• CPC Class Codes: H04L 49/103 using a shared central buffer; using a shared memory
• CPC Class Codes: H04L 49/201 Multicast operation; Broadcast operation
• CPC Class Codes: H04L 49/25 Routing or path finding in a switch fabric
• CPC Class Codes: H04L 49/255 Control mechanisms for ATM switching fabrics
• CPC Class Codes: H04L 49/30 Peripheral units, e.g. input or output ports
• CPC Class Codes: H04L 49/3009 Header conversion, routing tables or routing tags
• CPC Class Codes: H04L 49/3027 Output queuing
• CPC Class Codes: H04L 49/3054 Auto-negotiation, e.g. access control between switch gigabit interface connector [GBIC] and link
• CPC Class Codes: H04L 49/351 for local area network [LAN], e.g. Ethernet switches
• CPC Class Codes: H04L 49/354 for supporting virtual local area networks [VLAN]
• CPC Class Codes: H04L 49/40 : Constructional details, e.g. power supply, mechanical construction or backplane
• CPC Class Codes: H04L 49/50 : Overload detection or protection within a single switching element
• CPC Class Codes: H04L 49/552 : by ensuring the integrity of packets received through redundant connections
• CPC Class Codes: H04L 49/555 : Error detection
• CPC Class Codes: H04L 49/90 : Buffering arrangements
• CPC Class Codes: H04L 49/901 : using storage descriptor, e.g. read or write pointers
• CPC Class Codes: H04L 49/9047 : including multiple buffers, e.g. buffer pools
• CPC Class Codes: H04L 49/9063 : Intermediate storage in different physical parts of a node or terminal
• CPC Class Codes: H04L 49/9073 : Early interruption upon arrival of a fraction of a packet
• CPC Class Codes: H04L 49/9078 : using an external memory or storage device
• CPC Class Codes: H04L 49/9084 : Reactions to storage capacity overflow
• CPC Class Codes: H04Q 2213/1316 : Service observation, testing
• CPC Class Codes: H04Q 2213/13162 : Fault indication and localisation
• CPC Class Codes: H04Q 3/54591 : Supervision, e.g. fault localisation, traffic measurements, avoiding errors, failure recovery, monitoring, statistical analysis

Abstract

Management data is selectively supplied to a management agent by a network switch using either a media access control (MAC) layer interface or PCI bus interface to provide maximum flexibility for the management agent. The management data includes management packets having at least a portion of a received data packet, and management information specifying receive status and network switch response characteristics to the corresponding received data packet. The network switch includes a plurality of network ports, including network traffic ports and one management queue for selectively supplying the management data to either the PCI interface or the management MAC interface. The selective output of the management frame via the alternate output paths enables the disclosed network switch to be implemented in existing switch fabric that uses a predetermined management protocol. The paths may also be segregated to optimize bandwidth for high priority data and low priority data, respectively.

Claims

1. A network switch comprising:

a PCI bus interface configured for enabling access by a host to the network switch;

a media access control (MAC) layer interface configured for sending and receiving data frames to and from the host; and

a first output buffer configured for selectively outputting data for the host via one of the MAC layer interface and the PCI bus interface.

2. The switch of claim 1, further comprising a buffer configuration register accessible by the host for setting the first output buffer to output the data to one of the MAC layer interface and the PCI bus interface.

3. The switch of claim 1, further comprising a second output buffer for storing high priority data, the host accessing the high priority data via the PCI interface and selectively controlling output of management data from the first output buffer via one of the PCI bus interface and the MAC layer interface.

4. The switch of claim 3, further comprising an external memory interface configured for supplying and retrieving data to and from an external memory, the first output buffer storing management frame pointers and the second output buffer storing high priority frame pointers, the management frame pointers and the high priority frame pointers identifying external memory locations of the management data and high priority data, respectively.

5. The switch of claim 4, further comprising a buffer manager configured for retrieving at least a portion of the management data via the external memory interface based on a corresponding management frame pointer retrieved from the first output buffer, the MAC layer interface sending the at least a portion of the retrieved management data in one of said data frames to the host.

6. The switch of claim 4, wherein the second output buffer outputs the high priority frame pointers to the PCI bus interface in response to a PCI access of the second output buffer by the host.

7. The switch of claim 6, wherein the PCI bus interface is configured to enable a PCI access by the host to the external memory locations specified by the high priority frame pointers accessed by the host via the external memory interface.

8. The switch of claim 4, wherein the first output buffer stores for each of the management frame pointers a corresponding set of management status fields.

9. The switch of claim 8, wherein the management status fields include an operational code specifying characteristics of the corresponding management data, and a switching memory index pointer specifying a memory location of switching information for a received data frame corresponding to the management data.

10. The switch of claim 1, further comprising:

an external memory interface configured for supplying and retrieving data to and from external memory locations based on respective frame pointers;

a plurality of output buffers serving a plurality of said MAC layer interfaces, respectively; and

a port vector manager, accessible by the host via the PCI bus interface, for supplying a specified frame pointer to a specified plurality of the output ports.

11. The switch of claim 10, wherein the port vector manager receives the specified frame pointer and a port vector from the host via the PCI bus interface, the port vector identifying the specified plurality of the output ports, the port vector manager supplying the specified frame pointer to the specified plurality of the output ports based on the received port vector.

12. A system comprising:

a host processor having a host PCI bus interface and a host media access layer (MAC) interface;

a network switch configured for sending and receiving data packets to and from network stations, the network switch comprising;

(1) a PCI bus interface in communication with the host PCI bus interface and configured for enabling access by the host to the network switch;

(2) a media access control (MAC) layer interface sending and receiving data frames to and from the host MAC interface; and

(3) a first output buffer configured for selectively outputting data to the host via one of the MAC layer interface and the PCI bus interface.

13. The system of claim 12, wherein:

the system further comprises an external memory configured for storing data in respective identified memory locations, the data including received data packets and receive data identifying reception characteristics of the received data packets, respectively;

the network switch further comprises an external memory interface for accessing the external memory, the network switch configured for accessing selected data based on a frame pointer specifying the corresponding identified memory location.

14. The system of claim 13, wherein the host accesses selected data from the external memory based on retrieval of the corresponding frame pointer.

15. The system of claim 14, wherein the first output buffer stores management data fields for each corresponding frame pointer, the host retrieving the frame pointer and the corresponding management data from the first output buffer via the PCI interface.

16. The system of claim 13, wherein the first output buffer comprises a first buffer portion and a MAC transmit buffer portion, the first buffer portion storing said frame pointer and corresponding status fields, the MAC transmit buffer portion configured for storing, for each packet to be transmitted by the MAC layer interface, the corresponding management status fields, the corresponding receive data, and at least a portion of the corresponding received data packet.

17. The system of claim 16, wherein the network switch further comprises a second output buffer for storing second frame pointers specifying storage locations of expansion bus data in the external memory, the host accessing the second frame pointers from the second output buffer via the PCI interface and transferring the expansion bus data from the external memory to an expansion bus based on the corresponding retrieved second frame pointers.

18. The system of claim 16, wherein the management status fields for each corresponding received data packet include an operational code specifying corresponding characteristics, and a switching index pointer for identifying corresponding switching information.

19. The system of claim 16, wherein the host accesses the frame pointer and the corresponding status fields from the first buffer portion via the PCI interface.

20. The system of claim 13, wherein the network switch further comprises a second output buffer for storing second frame pointers specifying storage locations of expansion bus data in the external memory, the host accessing the second frame pointers from the second output buffer via the PCI interface and transferring the expansion bus data from the external memory to an expansion bus based on the corresponding retrieved second frame pointers.

21. A method in a network switch comprising:

storing data to be output to a host controlling the network switch in a first output buffer;

selecting one of a PCI interface and a media access control (MAC) layer interface as an output path for the data to be output; and

outputting the data to the host via the selected output path, wherein

the selecting step comprises setting the output path in response to the host setting a path configuration in the network switch.

22. A method in a network switch comprising:

storing data to be output to a host controlling the network switch in a first output buffer;

selecting one of a PCI interface and a media access control (MAC) layer interface as an output path for the data to be output; and

outputting the data to the host via the selected output path, wherein;

the first output buffer includes a first buffer portion and a MAC transmit buffer portion; and

the storing step comprises;

(1) storing a frame pointer, specifying a storage location of a data packet to be output to the host, and management status fields corresponding to the data packet to be output, and (2) selectively storing the management status fields and at least a portion of the data packet in the MAC transmit buffer portion based on the corresponding frame pointer.

23. The method of claim 22, wherein the outputting step comprises:

(1) outputting the frame pointer and the management status fields from the first buffer portion to the host via the PCI interface if the PCI interface is the selected output path; and

(2) outputting from the MAC transmit buffer portion the management status fields and the at least a portion of the data packet if the MAC layer interface is the selected output path.

24. The method of claim 22, further comprising storing in an external memory at the storage location specified by the frame pointer the data packet to be output to the host and corresponding receive data;

and

wherein the first output buffer storing step further comprises (3) accessing the frame pointer from the first buffer portion, and (4) transferring the management status fields, the at least a portion of the data packet, and the corresponding receive data in the MAC transmit buffer portion based on the accessed frame pointer.

25. The method of claim 22, further comprising storing in an external memory at the storage location specified by the frame pointer the data packet to be output to the host and corresponding receive data;

wherein the outputting step comprises enabling access of the storage location in the external memory by the host via the PCI interface.