Shared memory initialization method for system having multiple processor capability

• US 6,158,000 A
• Filed: 09/18/1998
• Issued: 12/05/2000
• Est. Priority Date: 09/18/1998
• Status: Expired due to Term

• Current Assignee: Hewlett Packard Enterprise Development LP (Hewlett-Packard Enterprise Company)
• Original Assignee: Compaq Computer Corporation (HP Inc.)
• Inventors: Collins, David L.
• Primary Examiner(s): Grant, William
• Assistant Examiner(s): Hartman, Jr., Ronald D
• Application Number:
  US09/158,165
• Time in Patent Office: 809 Days
• Field of Search: 713/1, 713/2, 712/21
• US Class Current: 713/1
• CPC Class Codes: G06F 15/177 Initialisation or configuration control processor initialisation G06F9/4405
• CPC Class Codes: G06F 9/4405 Initialisation of multiprocessor systems

Abstract

A multiprocessor computer system is provided with a BIOS that allows parallel execution of system initialization tasks by at least two processors to reduce system boot-up time. At power-on, one of the processors is designated as a bootstrap processor and the remaining processors are designates as application processors. The processors are coupled to a shared memory module by a shared processor bus. The bootstrap processor is configured to instruct the application processor to test and initialize memory locations in the shared memory module while the bootstrap processor proceeds with other system initialization tasks which may include determining the system configuration, initializing peripheral devices, testing the keyboard, and setting up the BIOS data area with configuration information. After completing its tasks, the bootstrap processor determines whether the application processor has completed the memory test, and if so, the bootstrap processor proceeds to locate and execute an operating system. It is expected that testing and initializing memory in parallel with other system initialization tasks will advantageously reduce system boot-up time in multiprocessor systems having large memories (e.g. 1-4 gigabytes).

Claims

1. A computer system which comprises:

a shared memory module that includes a plurality of memory locations;

an application processor coupled to the shared memory module by a shared processor bus; and

a bootstrap processor coupled to the memory module by the shared processor bus and coupled to the application processor,

wherein the bootstrap processor is configured to instruct the application processor to test the plurality of memory locations in the shared memory module after system power-on,

wherein the bootstrap processor is configured to perform a plurality of POST tasks while the application processor is testing the plurality of memory locations,

and wherein the bootstrap processor is further configured to execute a bootstrap loader after determining that the application processor has tested the plurality of memory locations.

2. The computer system of claim 1, wherein said plurality of POST tasks includes initializing peripheral devices.

3. The computer system of claim 2, wherein one of said peripheral devices is a PCI device, and wherein said initialization includes determining a PCI device address.

4. The computer system of claim 1, wherein said plurality of POST tasks includes verifying the system configuration.

5. The computer system of claim 1, wherein said plurality of POST tasks includes a keyboard test.

6. The computer system of claim 1, wherein said plurality of POST tasks includes setting up a BIOS data area in the shared memory module, and wherein said BIOS data area stores system configuration information.

7. The computer system of claim 1, wherein said plurality of POST tasks includes configuring a hard disk drive controller.

8. The computer system of claim 1, wherein the application processor is configured to test the plurality of memory locations in response to an instruction from the bootstrap processor, and further configured to store test results in the shared memory module for the bootstrap processor to read.

9. The computer system of claim 1, wherein the plurality of memory locations comprises all memory locations after a first megabyte (1048576 bytes) of memory in the shared memory module.

10. A method for booting-up a computer system, wherein the method comprises:

resetting a plurality of processors;

determining a bootstrap processor from the plurality of processors, wherein any remaining processors are designated as application processors;

the bootstrap processor instructing an application processor to test a plurality of memory locations in a shared memory module;

the bootstrap processor performing POST tasks while the application processor tests the plurality of memory locations; and

the bootstrap processor searching for an operating system to load into the shared memory module after the application processor finishes testing the plurality of memory locations.

11. The method of claim 10, wherein the POST tasks performed by the bootstrap processor while the application processor tests the plurality of memory locations include initializing peripheral devices.

12. The method of claim 10, wherein the POST tasks performed by the bootstrap processor while the application processor tests the plurality of memory locations include verifying a system configuration.

13. The method of claim 10, wherein the plurality of memory locations comprises all memory locations after a first megabyte (1048576 bytes) of memory in the shared memory module.

14. A multiprocessor system which comprises:

a shared memory module which requires initialization after system power-on;

a plurality of processors coupled to the shared memory module to store and retrieve executable programs and data, wherein each of the plurality of processors is reset after system power-on and thereafter participates in an arbitration process to determine a bootstrap processor from the plurality of processors, and wherein any remaining processors from the plurality of processors are designated as application processors; and

a nonvolatile memory coupled to the plurality of processors and configured to store a BIOS for retrieval by any of the processors, wherein the BIOS includes instructions for the bootstrap processor to direct an application processor to test a plurality of memory locations in the shared memory module,

wherein the BIOS further includes instructions for the bootstrap processor to conduct one or more POST tasks while the application processor tests the plurality of memory locations.

15. The multiprocessor system of claim 14, wherein the one or more POST tasks includes initializing peripheral devices.

16. The multiprocessor system of claim 14, wherein the one or more POST tasks includes determining a system configuration.

17. The multiprocessor system of claim 14, wherein the plurality of memory locations comprises all memory locations after a first megabyte (1048576 bytes) of memory in the shared memory module.

18. The multiprocessor system of claim 14, wherein the BIOS further includes instructions for determining when the application processor has finished testing the plurality of memory locations, and includes instructions for the bootstrap processor to locate and run an operating system after the application processor has finished testing the plurality of memory locations.

19. A computer system which comprises:

a volatile system memory having memory locations for temporarily storing data;

at least two processors coupled to the system memory to read and write said data;

a power switch;

a power supply coupled to the power switch to detect operation of the power switch, and coupled to provide power to the system memory and the processors in response to operation of the power switch, wherein the power supply is configured to assert a reset signal for a predetermined time after an initial operation of the power switch,

wherein the processors are configured to receive the reset signal and configured to enter arbitration in response to assertion of the reset signal to select one of the processors as a bootstrap processor and to identify remaining processors as application processors,

wherein the bootstrap processor is further configured to instruct at least one application processor to test memory locations in the system memory module,

wherein the bootstrap processor is further configured to initialize peripheral devices while the memory is being tested by at least one application processor.

20. The computer system of claim 19, wherein the processors and system memory are coupled together by a shared processor bus.

21. A computer system which comprises:

a shared memory module consisting of a base portion and a remaining portion, each having a plurality of memory locations;

an application processor coupled to the shared memory module by a shared processor bus; and

a bootstrap processor coupled to the memory module by the shared processor bus,

wherein after the bootstrap processor tests the base portion of the shared memory module, the bootstrap processor instructs the application processor to test the remaining portion of the shared memory module,

wherein the bootstrap processor is configured to perform a plurality of POST tasks while the application processor is testing the remaining portion of the shared memory module.

22. The computer system of claim 21, wherein said plurality of POST tasks includes initializing peripheral devices.

23. The computer system of claim 21, wherein said plurality of POST tasks includes verifying the system configuration.

24. The computer system of claim 21, wherein the application processor is configured to test the remaining portion of the shared memory module in response to an instruction from the bootstrap processor, and is further configured to store test results in the shared memory module for the bootstrap processor to read.

25. The computer system of claim 21, wherein the remaining portion of the shared memory module comprises all memory locations after a first megabyte (1048576 bytes) of memory in the shared memory module.