Active pixel sensor array with simple floating gate pixels

• US 6,166,768 A
• Filed: 01/22/1997
• Issued: 12/26/2000
• Est. Priority Date: 01/28/1994
• Status: Expired due to Term

• Current Assignee: California Institute of Technology
• Original Assignee: California Institute of Technology
• Inventors: Kemeny, Sabrina E., Fossum, Eric R., Nakamura, Junichi
• Primary Examiner(s): Garber, Wendy
• Assistant Examiner(s): White, Mitchell
• Application Number:
  US08/785,931
• Time in Patent Office: 1,434 Days
• Field of Search: 348/241, 348/250, 348/302, 348/304, 348/308, 348/309, 257/239
• US Class Current: 348/308
• CPC Class Codes: G11C 19/282 with charge storage in a depletion layer, i.e. charge coupled devices [CCD]
• CPC Class Codes: G11C 19/285 Peripheral circuits, e.g. for writing into the first stage; for reading-out of the last stage
• CPC Class Codes: H01L 27/14621 Colour filter arrangements
• CPC Class Codes: H01L 27/14627 Microlenses
• CPC Class Codes: H01L 27/14645 Colour imagers
• CPC Class Codes: H01L 27/14843 Interline transfer
• CPC Class Codes: H01L 27/1485 Frame transfer
• CPC Class Codes: H01L 27/14856 Time-delay and integration
• CPC Class Codes: H01L 27/14868 CCD or CID colour imagers
• CPC Class Codes: H01L 27/14887 Blooming suppression
• CPC Class Codes: H01L 31/02162 for filtering or shielding light, e.g. multicolour filters for photodetectors
• CPC Class Codes: H01L 31/0232 Optical elements or arrangements associated with the device H01L31/0236 takes precedence; for photovoltaic cells H01L31/054; for photovoltaic modules H02S40/20
• CPC Class Codes: H04N 23/10 for generating image signals from different wavelengths
• CPC Class Codes: H04N 25/53 Control of the integration time
• CPC Class Codes: H04N 25/531 by controlling rolling shutters in CMOS SSIS
• CPC Class Codes: H04N 25/616 involving a correlated sampling function, e.g. correlated double sampling [CDS] or triple sampling
• CPC Class Codes: H04N 25/63 applied to dark current
• CPC Class Codes: H04N 25/65 applied to reset noise, e.g. KTC noise related to CMOS structures by techniques other than CDS
• CPC Class Codes: H04N 25/77 Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components

Abstract

An imaging device formed as a monolithic complementary metal oxide semiconductor integrated circuit in an industry standard complementary metal oxide semiconductor process, the integrated circuit including a focal plane array of pixel cells, each one of the cells including a photogate overlying the substrate for accumulating photo-generated charge in an underlying portion of the substrate and a charge coupled device section formed on the substrate adjacent the photogate having a sensing node and at least one charge coupled device stage for transferring charge from the underlying portion of the substrate to the sensing node. There is also a readout circuit, part of which can be disposed at the bottom of each column of cells and be common to all the cells in the column. A Simple Floating Gate (SFG) pixel structure could also be employed in the imager to provide a non-destructive readout and smaller pixel sizes.

Claims

1. An imaging device comprising:

a monolithic semiconductor integrated circuit substrate;

a focal plane array of pixel cells, each one of said pixel cells comprising;

a photogate electrode, overlying a photogate portion of said substrate, and capable of accumulating photo-generated charge in an underlying portion of said substrate, and

a charge coupled device section formed on said substrate adjacent said photogate portion, having an output transistor whose gate is connected to said photogate electrode to form a floating gate to produce an electrical signal indicative of said photo-generated charge and at least one charge coupled device stage capable of transferring charge from said underlying portion of the substrate to a drain of said output transistor during a reset operation.

2. The imaging device of claim 1 wherein:

said charge coupled device stage comprises a transfer gate between said drain of said output transistor and said photogate.

3. The imaging device of claim 2, wherein said charge coupled device section includes a capacitor having a first terminal coupled to both said floating gate of said output transistor and said photogate electrode and a second terminal to receive a row address voltage signal that is at an integration voltage higher than a barrier potential at said transfer gate during an integration period and is at a readout voltage which is higher than said integration voltage during a readout period.

4. The imaging device of claim 1 further comprising:

means for periodically resetting a potential of said floating gate to a predetermined potential.

5. The imaging device of claim 1, wherein each one of said pixel cells further comprises:

a drain diffusion connected to a drain bias voltage; and

a reset gate between said sensing node and said drain diffusion, said reset gate connected to a reset control signal.

6. The imaging device of claim 1, further comprising:

a readout circuit comprising a field effect source follower output transistor having a gate coupled to receive an output from said floating gate of said output transistor.

7. The imaging device of claim 6, wherein said readout circuit further comprises:

a field effect load transistor connected to said source follower output transistor.

8. The imaging device of claim 7, wherein said readout circuit further comprises:

a correlated double sampling circuit having an input node connected between said source follower output transistor and said load transistor.

9. The imaging device of claim 8, wherein the correlated double sampling circuit comprises:

a pair of sample and hold field effect transistors formed in said substrate, each sample and hold field effect transistor having one of a source and drain thereof connected to a source of said source follower transistor;

a pair of sample and hold capacitors connected to the other one of the source and drain of a respective one of said pair of sample and hold transistors; and

means for sensing a potential of each of said sample and hold capacitors at respective intervals.

10. The imaging device of claim 9 further comprising:

means for sensing a difference between potentials of said pair of sample and hold capacitors.

11. The imaging device of claim 9 further comprising:

means for shorting across each of said pair of sample and hold capacitors simultaneously while said means for sensing measures a fixed pattern noise difference.

12. The imaging device of claim 9, wherein said focal array of cells is organized by rows and columns of said cells, and wherein said readout circuit further comprises:

plural load transistors and plural correlated double sampling circuits, wherein each cell in each column of cells is connected to a single common load transistor and a single common correlated double sampling circuit.

13. The imaging device of claim 12, wherein:

each of said common load transistors and correlated double sampling circuits is disposed at the bottom of said respective columns of cells connected thereto.

14. The imaging device of claim 12, the readout circuit further comprises:

a row select field effect transistor formed in each one of said cells having its source and drain connected between said source of said source follower output transistor and said pair of sample and hold transistors, and a gate connected to a row select signal; and

wherein

said means for sensing at period intervals comprises,

a pair of sample and hold output transistors having respective gates and sources connected across respective ones of said pair of sample and hold capacitors, and having respective drains,

respective differential output nodes of said correlated double sampling circuit, and

a pair of column select transistors formed in said substrate each having a source and drain connected between a drain of a respective one of said sample and hold output transistors and a gate connected to a column select signal.

15. The imaging device of claim 14 wherein:

each of said transistors is a metal oxide field effect transistor, said source follower output transistor, said load transistor, said row select transistor, and said pair of sample and hold transistors being n-channel devices, said pair of sample and hold output transistors and said pair of column select transistors being p-channel devices.

16. The imaging device of claim 1 further comprising a micro-lens layer overlying said substrate, said micro-lens layer comprising:

a refractive layer; and

individual lenses formed in said layer in registration with individual ones of said cells, each of said individual lenses having a curvature for focusing light toward a photosensitive portion of the respective cell.

17. The imaging device of claim 16, wherein:

said refractive layer comprises a polymer.

18. The imaging device of claim 17 wherein:

said refractive layer comprises polyamide.

19. The imaging device of claim 16, wherein

each of said individual lenses covers portions of the corresponding cell including said photogate as well as said charge coupled device section.

20. The imaging device of claim 1, further comprising CMOS image signal processing electronics integrated on said substrate and connected to communicate with said focal plane array, said CMOS image signal processing electronics providing on-chip signal processing of electrical signals from said pixel cells.

21. An imaging device comprising:

a monolithic semiconductor integrated circuit substrate;

a focal plane array of pixel cells formed on said substrate by an integrated circuit process that is compatible with a complementary metal oxide semiconductor (CMOS) process, each one of said pixel cells comprising,

a photogate electrode overlying said substrate and operable to accumulate photo-generated charge in an underlying photogate portion of said substrate,

a barrier gate formed on said substrate adjacent said photogate portion, and

a pixel transistor formed on said substrate and configured to have a first diffusion region adjacent said barrier gate, a gate and a second diffusion region, said gate connected to said photogate electrode to form a floating gate,

wherein said barrier gate is operable to transfer said photo-generated charge from said underlying photogate portion of said substrate to said first diffusion region of said pixel transistor, and wherein said gate of said pixel transistor produces an electrical signal comprising a signal component indicative of said photo-generated charge and a noise component indicative of noise associated with said pixel; and

MOS image signal processing electronics integrated on said substrate and connected to communicate with said focal plane array and to provide on-chip signal processing of electrical signals from said pixel cells.

22. The imaging device of claim 21, further comprising:

a readout circuit formed on said substrate and comprising a field-effect source follower output transistor coupled to receive said electrical signal from said pixel transistor;

a field-effect load transistor connected to said source follower output transistor; and

a correlated double sampling circuit having an input node connected between said source follower output transistor and said load transistor and operable to produce an output signal indicating only said photo-generated charge, wherein said sampling circuit samples said electrical signal once when said gate of said pixel transistor is set at a first gate potential without changing an amount of photo-generated charge in said first diffusion region and to sample said electrical signal for a second time when said gate of said pixel transistor is set at a second gate potential.

23. The imaging device of claim 21, wherein said first diffusion region is biased at a selected DC voltage to function as a drain.

24. An imaging device comprising:

a monolithic semiconductor integrated circuit substrate;

a focal plane array of pixel cells formed on said substrate by an integrated circuit process that is compatible with complementary metal oxide semiconductor (CMOS) process, each one of said pixel cells comprising,

a photogate overlying said substrate and operable to accumulate photo-generated charge in an underlying portion of said substrate,

a barrier gate formed on said substrate adjacent said photogate, and

a pixel transistor formed on said substrate and configured to have a drain adjacent said barrier gate, a gate and a source,

a capacitor having a terminal connected to both said photogate and said gate of said pixel transistor to make said gate of said pixel transistor a floating gate,

wherein said barrier gate is operable to transfer said photo-generated charge from said underlying portion of said substrate under said photogate to said drain of said pixel transistor which produces an electrical signal having a signal component indicative of said photo-generated charge.

25. The imaging device of claim 24, further comprising a readout circuit formed on said substratte to receive said electrical signal, said read circuit comprising:

a field-effect source follower output transistor coupled to receive said electrical signal;

a field-effect load transistor connected to said source follower output transistor; and

a correlated double sampling circuit having an input node connected between said source follower output transistor and said load transistor and operable to sample said second diffusion region twice in a readout operation to produce an output signal indicating only said photo-generated charge.

26. The imaging device of claim 24, further comprising CMOS image signal processing electronics integrated on said substrate and connected to communicate with said focal plane array, said CMOS image signal processing electronics providing on-chip signal processing of electrical signals from said pixel cells.

27. A method, comprising:

producing charge in a portion of a semiconductor substrate under a photogate electrode in response to incident photons incident to said portion;

using a transfer gate formed in said substrate next to said photogate to output said charge in said portion;

using a drain of an output transistor formed in said substrate next to said transfer gate to receive said charge from said portion; and

connecting a gate of said output transistor to said photogate to form a floating gate so as to convert said charge into an electrical signal.

28. A method as in claim 27, further comprising biasing said drain at a DC voltage.

29. A method as in claim 27, further comprising:

coupling a first terminal of a capacitor to both said photogate and said gate of said output transistor;

using a second terminal of said capacitor to receive a row address voltage; and

using a source of said output transistor to receive a row address voltage.

30. A method as in claim 29, further comprising:

setting said row address voltage at an integration voltage higher than a barrier potential at said transfer gate during an integration period; and

setting said row address voltage at a readout voltage which is higher than said integration voltage during a readout period.