Receive amplifier for high speed data

• US 6,169,454 B1
• Filed: 01/12/2000
• Issued: 01/02/2001
• Est. Priority Date: 03/04/1998
• Status: Expired due to Term

• Current Assignee: Ciena Corporation
• Original Assignee: Nortel Networks Limited (Nortel Networks Corporation)
• Inventors: Hogeboom, John Gordon
• Primary Examiner(s): Shingleton, Michael B
• Application Number:
  US09/481,907
• Time in Patent Office: 356 Days
• Field of Search: 330/252, 330/253, 330/258, 330/259, 330/9, 330/277, 330/255
• US Class Current: 330/258
• CPC Class Codes: H03K 5/2481 with at least one differential stage
• CPC Class Codes: H04L 25/0274 Arrangements for ensuring balanced coupling
• CPC Class Codes: H04L 25/0292 Arrangements specific to the receiver end

Abstract

A receive amplifier for high-speed data has a differential input stage with a very wide common-mode rejection range and low offset voltage. This input stage interfaces the differential data signals to be received. The input stage is a dual complementary differential configuration of ten MOS transistors preferably connected to provide a pair of differential inputs, a pair of differential outputs, and a single common-mode feedback input. The latter feedback input is used in the preferred embodiment to achieve balance and high common-mode rejection. Two-transistor CMOS inverters are preferably used both as amplifying stages after the input stage and as a feedback amplifier. In alternative embodiments, the nodes connected to the feedback input are instead reconnected to fixed voltages, typically one of the supply voltages or a fixed intermediate voltage, to form two independent amplifiers, one for each input node.

Claims

1. A receive amplifier circuit for reception of data signals on a channel, said receive amplifier having a relatively positive supply voltage and a relatively negative supply voltage, said receive amplifier comprising in combination:

a) an input stage responsive to the data signals, said input stage comprising;

two independent complementary amplifiers, each amplifier associated with two complementary load devices,

a pair of common-gate-bias nodes,

said two complementary load devices having gates connected to a respective common-gate-bias node;

b) a pair of complementary output terminals for output of amplified data signals; and

c) two current-limiting devices, each current-limiting device connected to the two complementary load devices of a respective one of the amplifiers, each current-limiting device including a gate connected to a respective common-gate-bias node;

d) each of said common-gate-bias nodes being connected to a predetermined fixed voltage.

2. A receive amplifier circuit as recited in claim 1, wherein each of said differential pairs is formed by a complementary pair of transistors.

3. A receive amplifier circuit as recited in claim 1, further comprising at least two gain amplifiers connected in series with said complementary output terminals.

4. A receive amplifier circuit as recited in claim 2, wherein said complementary pair of transistors comprises CMOS transistors.

5. A receive amplifier circuit as recited in claim 3, wherein said at least two gain amplifiers comprise negative feedback amplifiers.

6. A receive amplifier circuit as recited in claim 3, wherein said at least two gain amplifiers comprise CMOS inverters.

7. A receive amplifier circuit as recited in claim 1, wherein said predetermined fixed voltage equals the relatively positive supply voltage.

8. A receive amplifier circuit as recited in claim 1, wherein said predetermined fixed voltage equals the relatively negative supply voltage.

9. A receive amplifier circuit as recited in claim 1, wherein said predetermined fixed voltage is intermediate between the relatively positive supply voltage and the relatively negative supply voltage for setting the input switching point of said receive amplifier.