MOS transistor with shield coplanar with gate electrode

• US 6,172,400 B1
• Filed: 08/25/1998
• Issued: 01/09/2001
• Est. Priority Date: 04/27/1998
• Status: Expired due to Fees

• Current Assignee: Hanger Solutions, LLC (IP Investments Group LLC)
• Original Assignee: Spectrian Corp. (REMEC, Inc.)
• Inventors: Hebert, Francois, Ng, Sze Him
• Primary Examiner(s): Saadat, Mahshid
• Assistant Examiner(s): Fenty, Jesse A.
• Application Number:
  US09/139,532
• Time in Patent Office: 868 Days
• Field of Search: 257/343, 257/409, 257/488, 257/340, 257/365, 257/331, 257/353
• US Class Current: 257/343
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/7801 DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region lateral high-voltage MISFETs with channel well and drain offset region H01L29/7835
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7816 Lateral DMOS transistors, i.e. LDMOS transistors
• CPC Class Codes: H01L 29/7835 with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs

Abstract

A MOS transistor including a gate electrode on a gate oxide over a channel region between a source region and a drain region also includes a shield electrode at least partially on the gate oxide adjacent to, self-aligned with, and at least partially coplanar with the gate electrode and between the gate electrode and drain region. Placing the shield electrode on the gate oxide improves the gate-drain shielding, reduces the gate-drain capacitance, Cgd, and reduces hot electron related reliability hazard.

Claims

1. A MOS transistor comprising:

a) a silicon substrate of one conductivity type,

b) a well region of a second conductivity type in a surface of the substrate,

c) source region and a channel region in the well region,

d) a gate oxide layer on the surface of the well region,

e) a gate electrode on the gate oxide layer with at least a portion of the gate electrode being over the channel region, and

f) a shield electrode on the gate oxide layer adjacent to and spaced from the gate electrode and at least partially coplanar with the portion of the gate electrode over the channel.

2. The MOS transistor as defined by claim 1 and further including a drain region separated from the source region by the channel region.

3. The MOS transistor as defined by claim 2 wherein the drain region is in the well region, the shield electrode being positioned between the gate electrode and the drain region.

4. The MOS transistor as defined by claim 3 wherein the oxide layer under the shield electrode is thicker adjacent to the drain region than the oxide layer adjacent the channel region.

5. The MOS transistor as defined by claim 4 and further including a metal electrode contacting the source region and a metal electrode contacting the drain region.

6. The MOS transistor as defined by claim 5 and further including a metal electrode contacting the shield electrode.

7. The MOS transistor as defined by claim 6 and further including a passivating dielectric layer over the surface of the transistor.