Memory circuit

• US 6,172,936 B1
• Filed: 02/24/1999
• Issued: 01/09/2001
• Est. Priority Date: 05/28/1998
• Status: Expired due to Term

• Current Assignee: Socionext Inc.
• Original Assignee: Fujitsu Limited
• Inventors: Kitazaki, Kazuhiro
• Primary Examiner(s): Elms, Richard
• Assistant Examiner(s): NGUYEN, VAN THU T
• Application Number:
  US09/256,087
• Time in Patent Office: 685 Days
• Field of Search: 365/185.33, 365/233, 365/226, 327/142, 327/143, 711/103, 711/167, 711/166
• US Class Current: 365/233.17
• CPC Class Codes: G11C 7/1015 Read-write modes for single port memories, i.e. having either a random port or a serial port
• CPC Class Codes: G11C 7/1018 Serial bit line access mode, e.g. using bit line address shift registers, bit line address counters, bit line burst counters
• CPC Class Codes: G11C 7/1027 Static column decode serial bit line access mode, i.e. using an enabled row address stroke pulse with its associated word line address and a sequence of enabled bit line addresses
• CPC Class Codes: G11C 7/1033 using data registers of which only one stage is addressed for sequentially outputting data from a predetermined number of stages, e.g. nibble read-write mode
• CPC Class Codes: G11C 7/1045 Read-write mode select circuits
• CPC Class Codes: G11C 7/1072 for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories

Abstract

The present invention comprises a flash memory or similar nonvolatile memory circuit characterized by a constitution that enables read operations in two modes, a clock-synchronous burst read mode and a clock-asynchronous normal read mode, the device being set to normal read mode in response to power on, and being set to burst read mode in response to a control signal instructing the burst read mode. The memory device includes a burst mode switching circuit internally. This burst mode switching circuit sets an output circuit to normal read mode in response to the power ON so as to enable read operations not synchronized with the clock after the power ON. In response to a burst mode control signal provided by the system, the burst mode switching circuit sets the output circuit to burst read mode. Thus, the system can perform the burst read to the nonvolatile memory device under the environment analogous to conventional main memory access.

Claims

1. A memory circuit including nonvolatile memory cells, comprising:

an output circuit for executing clock-synchronous burst read operation and clock-asynchronous normal read operation of data read from the memory cells; and

a burst mode switching circuit for setting the output circuit to the normal read mode in response to power ON, and for setting the output circuit to the burst read mode in response to a specific control signal provided from outside.

2. The memory circuit according to claim 1, wherein the burst mode switching circuit sets the output circuit to the normal read mode in response to a reset operation.

3. The memory circuit according to claim 1 or 2, wherein the burst mode switching circuit comprises a latch circuit for supplying a burst control signal to the output circuit and latching the burst control signal in a burst read state when the burst read mode is set.

4. The memory circuit according to claim 1, wherein the burst mode switching circuit set into the normal read mode in response to an externally provided erase or write control signal.

5. The memory circuit according to claim 1, further comprising a plurality of input terminals,

wherein the burst mode switching circuit assumes mode-switching status in response to a specific command presented to at least one of the plurality of input terminals, and when placed in mode-switching status, in response to a mode switching signal supplied to any of the plurality of input terminals, switches the output circuit between the burst read mode and the normal read mode corresponding to the mode switching signal.

6. A memory circuit switchable in response to a burst control signal between a clock-synchronous first read mode and a clock-asynchronous second read mode:

wherein, in the first read mode, address signals are acquired in synchronous with a clock during a first control signal being at activation level, and a plurality of read data are output in synchronous with the clock during a second control signal being at activation level after a prescribed time interval after the first control signal being at the activation level;

comprising a burst mode switching circuit for setting the burst control signal to the second read mode condition when the power is turned on, and for setting the burst control signal to the first read mode condition in response to the first control signal being at the activation level.

7. The memory circuit according to claim 6, wherein the burst mode switching circuit sets the burst control signal to the second read mode in response to a reset operation.

8. The memory circuit according to claim 6, further comprising a plurality of input terminals,

wherein, with a third control signal at activation level, memory cells are erased or written to in response to an erase or write command presented to at least one of the plurality of input terminals; and the burst mode switching circuit sets the burst control signal to the second read mode state in response to the third control signal at the activation level.

9. The memory circuit according to claim 8, wherein, with the third control signal at the activation level, the burst mode switching circuit assumes a mode-switching state in response to a specific command presented to at least one of the plurality of input terminals, and when placed in mode-switching status, in response to a mode switching signal supplied to any of the plurality of input terminals, switches the burst control signal to the first or second read mode state corresponding to the mode switching signal.

10. The memory circuit according to any of claims 6 through 9, provided with nonvolatile memory for holding stored data with the power off.