Silicon oxide dielectric material with excess silicon as diffusion barrier layer
DCFirst Claim
1. A method for forming upon a substrate employed within a microelectronics fabrication an inter-level metal dielectric (IMD) layer comprising:
- providing a substrate;
forming upon the substrate a patterned microelectronics layer;
forming over the substrate a dielectric layer;
forming over the dielectric layer a silicon rich silicon oxide diffusion barrier dielectric layer; and
forming over the substrate a patterned conductor layer.
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Abstract
A method for forming upon a substrate employed within a microelectronics fabrication a first dielectric layer, an intermediate diffusion barrier dielectric layer and a conductor layer which comprise an inter-level metal dielectric (IMD) layer with attenuated diffusion between the dielectric layers and conductor layer. There is first provided a substrate employed within a microelectronics fabrication. There is then formed upon the substrate a patterned microelectronics layer. There is then formed over the substrate a first dielectric layer. There is then formed over the substrate a diffusion barrier dielectric layer. There is then formed over the substrate a conductor layer to complete an inter-level metal dielectric (IMD) layer with attenuated inter-diffusion between the dielectric layers and conductor layer.
25 Citations
18 Claims
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1. A method for forming upon a substrate employed within a microelectronics fabrication an inter-level metal dielectric (IMD) layer comprising:
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providing a substrate;
forming upon the substrate a patterned microelectronics layer;
forming over the substrate a dielectric layer;
forming over the dielectric layer a silicon rich silicon oxide diffusion barrier dielectric layer; and
forming over the substrate a patterned conductor layer. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
integrated circuit microelectronics fabrications;
charge coupled device microelectronics fabrications;
solar cell microelectronics fabrications;
optoelectronics microelectronics fabrications;
ceramic substrate microelectronics fabrications; and
flat panel display microelectronics fabrications.
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4. The method of claim 1 wherein the patterned microelectronics layer is selected from the group consisting of:
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microelectronics conductor layers;
microelectronics semiconductor layers; and
microelectronics dielectric layers.
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5. The method of claim 1 wherein the dielectric layer is formed employing a fluorine-doped silicon containing and/or carbon-containing dielectric material.
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6. The method of claim 1 wherein the diffusion barrier dielectric layer is formed employing plasma enhanced chemical vapor deposition (PECVD) of a silicon-rich silicon oxide dielectric material.
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7. The method of claim 6 wherein the silicon rich silicon oxide dielectric diffusion barrier layer material has a refractive index of from about 1.47 to about 1.8.
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8. The method of claim 1 wherein the patterned conductor layer is formed from copper or copper alloy conductor material.
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9. A method for forming upon a semiconductor substrate employed within an integrated circuit microelectronics fabrication an inter-level metal dielectric (IMD) layer comprising:
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providing a semiconductor substrate having formed therein a patterned microelectronics layer and a first dielectric layer employing fluorine-doped low dielectric constant dielectric material;
forming over the semiconductor substrate a silicon rich silicon oxide dielectric diffusion barrier layer;
forming over the substrate a second dielectric layer;
forming over the substrate a patterned photoresist etch mask layer and etching the pattern thereof into the second dielectric layer and diffusion barrier dielectric layer followed by stripping the photoresist etch mask layer;
filling the etched pattern with a copper conductor material; and
planarizing the surface of the second dielectric layer and copper layer. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16, 17, 18)
microelectronics conductor materials;
microelectronics semiconductor materials; and
microelectronics dielectric materials.
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13. The method of claim 9 wherein the first fluorine-containing low dielectric constant dielectric layer is formed from material selected from the group consisting of:
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fluorine-doped silicon containing glass (FSG) dielectric material;
fluorine-containing carbon containing dielectric material; and
fluorine-containing carbon and/or silicon containing dielectric material.
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14. The method of claim 9 wherein the silicon-rich silicon oxide dielectric layer is formed employing plasma enhanced chemical vapor deposition (PECVD).
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15. The method of claim 14 wherein the silicon rich silicon oxide dielectric material has a refractive index of from about 1.47 to about 1.8.
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16. The method of claim 9 wherein the second dielectric layer is formed employing dielectric material selected from the group consisting of:
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silicon containing dielectric material;
fluorine-containing silicon containing glass dielectric material;
fluorine-containing carbon containing dielectric material; and
fluorine-containing carbon and silicon containing dielectric material.
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17. The method of claim 9 wherein the copper containing conductor material is formed employing electrodeposition (ED) method.
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18. The method of claim 9 wherein the planarization process is a chemical mechanical polish (CMP) planarization process.
Specification