Channel encoding apparatus using single concatenated encoder

• US 6,182,260 B1
• Filed: 06/15/1998
• Issued: 01/30/2001
• Est. Priority Date: 06/16/1997
• Status: Expired due to Term

• Current Assignee: Electronics and Telecommunications Research Institute
• Original Assignee: Electronics and Telecommunications Research Institute
• Inventors: Kang, Bub Joo, Kim, Eung Bae, Park, Chae Min, Oh, Hyun Seo, Shim, Jae Ryong
• Primary Examiner(s): Baker, Stephen M.
• Application Number:
  US09/094,605
• Time in Patent Office: 960 Days
• Field of Search: 714/755, 714/761, 714/774
• US Class Current: 714/755
• CPC Class Codes: H03M 13/1515 Reed-Solomon codes
• CPC Class Codes: H03M 13/158 Finite field arithmetic processing
• CPC Class Codes: H03M 13/2903 Methods and arrangements specifically for encoding, e.g. parallel encoding of a plurality of constituent codes
• CPC Class Codes: H03M 13/2936 comprising an outer Reed-Solomon code and an inner convolutional code
• CPC Class Codes: H03M 13/6356 by repetition or insertion of dummy data, i.e. rate reduction

Abstract

Generally, Reed-Solomon encoding process in the conventional communication system is executed by a Reed-Solomon encoder having different code rates for different data transmission rates. The present invention does not use a Reed-Solomon encoder having different coding rates, but instead uses a Reed-Solomon encoder having the same code rate regardless of data transmission rate. Accordingly, the present invention has the following effects. The present invention maintains same communication quality regarding data services having each different data transmission rate, and can use a single Reed-Solomon encoder.

Claims

1. A channel encoding apparatus using a concatenated encoder, comprising:

a data block former for forming subdata blocks with constant size and grouped according to a plurality of different data transmission rates;

a serial/parallel converter for converting the subdata blocks formed by the data block former into several message symbols;

a Reed-Solomon encoder for outputting the message symbols converted by the serial/parallel converter, and computing several parity check symbols according to the message symbols to generate Reed-Solomon code symbols;

a parallel/serial converter for converting the Reed-Solomon code symbols generated by the Reed-Solomon encoder into serial data bits;

a zero tail adder for adding eight zero tail bits to the serial data bits from the parallel/serial converter; and

a convolutional encoder for convolutionally encoding the output data bits from the zero tail adder.

2. The channel encoding apparatus of claim 1, wherein the data block former includes a plurality of subdata block formers to form subdata blocks with 328 bits, respectively.

3. The channel encoding apparatus of claim 1, wherein the serial/parallel converter outputs 41 message symbols.

4. The channel encoding apparatus of claim 1, wherein the Reed-Solomon encoder outputs 47 Reed-Solomon code symbols.

5. The channel encoding apparatus of claim 1, wherein the Reed-Solomon encoder comprises:

a gate for transmitting message symbols outputted from the serial/parallel converter;

first to sixth multipliers for multiplying message symbols transmitted from the gate by predetermined coefficients, respectively;

a first 8-bit storage device for storing data outputted from the first multiplier;

a first exclusive OR gate for exclusive-ORing data stored in the first 8-bit storage device to data outputted from the second multiplier;

a second 8-bit storage device for storing data outputted from the first exclusive OR gate;

a second exclusive OR gate for exclusive-ORing data stored in the second 8-bit storage device to data outputted from the third multiplier;

a third 8-bit storage device for storing output data of the second exclusive OR gate;

a third exclusive OR gate for exclusive-ORing data stored in the third 8-bit storage device to output data of the fourth multiplier;

a fourth 8-bit storage device for storing output data of the third exclusive OR gate;

a fourth exclusive OR gate for exclusive-ORing data stored in the fourth 8-bit storage device to output data of the fifth multiplier;

a fifth 8-bit storage device for storing output data of the fourth exclusive OR gate;

a fifth exclusive OR gate for exclusive-ORing data stored in the fifth 8-bit storage device to output data of the sixth multiplier;

a sixth 8-bit storage device for storing output data of the fifth exclusive OR gate; and

a sixth exclusive OR gate for exclusive-ORing data stored in the fifth 8-bit storage device to message symbols of the serial/parallel converter to apply to the gate.

6. The channel encoding apparatus of claim 1, wherein the parallel/serial converter comprises an external interleaver which executes an external interleaving among subdata blocks corresponding to a 10 ms frame before converting Reed-Solomon code symbols into serial bits for data transmission rates over 65.6 kbps.

7. The channel encoding apparatus of claim 1, wherein the convolutional encoder has an encoding rate of ⅓

and a constraint length of 9.

8. The channel encoding apparatus of claim 1, wherein the convolutional encoder includes first to eighth 1-bit shift registers for successively storing output data of the zero tail adder;

a first exclusive OR gate for exclusive-ORing output data bits of the zero tail adder to output data bits of the second, third and fifth to eighth 1-bit shift registers to output first exclusive-ORed data bits;

a second exclusive OR gate for exclusive-ORing output data bits of the zero tail adder to output data bits of the first, third, fourth, and eighth 1-bit shift registers to output second exclusive-ORed data bits; and

a third exclusive OR gate for exclusive-ORing output data bits of the zero tail adder to output data bits of the first, second, fifth and eighth 1-bit shift registers to output third exclusive-ORed data bits.