Method and circuit for transporting data based on the content of ingress data words and egress data words

• US 6,185,635 B1
• Filed: 05/30/1998
• Issued: 02/06/2001
• Est. Priority Date: 05/30/1998
• Status: Expired due to Term

• Current Assignee: WSOU Investments, LLC (WSOU Holdings, LLC)
• Original Assignee: Alcatel Networks Incorporated (Nokia Corporation)
• Inventors: Patoine, Michel J. P., O'Loughlin, Gareth P., Smail, J. Morgan
• Primary Examiner(s): Lee, Thomas C.
• Assistant Examiner(s): PEYTON, TAMMARA R
• Application Number:
  US09/087,890
• Time in Patent Office: 983 Days
• Field of Search: 710/22, 710/11, 710/30, 710/60, 709/238, 370/364, 370/426
• US Class Current: 710/31
• CPC Class Codes: H04L 49/90 Buffering arrangements
• CPC Class Codes: H04L 49/9073 Early interruption upon arrival of a fraction of a packet
• CPC Class Codes: H04L 69/10 Streamlined, light-weight or high-speed protocols, e.g. express transfer protocol [XTP] or byte stream

Abstract

A method and apparatus for transporting data include processing that begins by receiving a bit stream of data at a rate of at least a bit per input interval. The bit stream of data corresponds to ingress packetized data that has been packetized based on one of a plurality of data packetizing protocols (e.g., HDLC encapsulated data, frame relay, PPP, and/or SMDS). As the bit stream is received, the data is extracted from the bit stream to produce extracted data, which is stored in ingress local memory. When a sufficient amount of extracted data is stored in the ingress local memory (i.e., an ingress data word is stored), it is transported to a non-local memory, where the transporting is based, at least in part, on content of the ingress data word. The processing also includes transporting stored egress data words from a non-local memory to an egress local memory based, at least in part, on content of the egress data words. The egress data words are then packetized based on a data packetizing protocol to produce egress packetized data. The egress packetized data is then outputted in a serial manner at the rate of at least one bit per output interval. The input and output intervals are based on time slot synchronization information, which, in turn, is based on at least one of a clock signal, the ingress data transport protocol, the egress data transport protocol.

Claims

1. A data transporting circuit comprises:

a data extraction module operably coupled to receive a bit stream of data at a rate of at least a bit per input interval, wherein the bit stream of data corresponds to ingress packetized data having one of a plurality of data packetizing protocols, and wherein the data extraction module extracts data from the bit stream of data to produce extracted data;

a data packetizing module operably coupled to receive stored data and to packetize the stored data based on a data packetizing protocol of the plurality of data packetizing protocols to produce egress packetized data, wherein the data packetizing module outputs the egress packetized data in a serial manner at a rate of at least a bit per output interval;

input/output control module operably coupled to the data extraction module and the data packetizing module, wherein the input/output module generates time slot synchronizing information based on at least one of a clock signal, an ingress data transport protocol, and an egress data transport protocol, and wherein the input interval and the output interval are based on the time slot synchronizing information; and

memory manager operably coupled to the data extraction module to transport the extracted data as ingress data words to a non-local memory for storage and to transport the stored data as egress data words from the non-local memory, wherein the memory manager transports the ingress data words and the egress data words based, at least in part, on content of ingress data words and the egress data words.

2. The data transporting circuit of claim 1, wherein the data extraction module comprises a plurality of data extraction sub-modules, wherein each of the plurality of data extraction sub-modules is coupled to receive at least a bit per input interval of respective portions of the bit stream.

3. The data transporting circuit of claim 1 further comprises a plurality of ingress multiplexors operably coupled to the plurality of data extraction sub-modules, wherein the plurality of ingress multiplexors are configuration based on an ingress data transport protocol such that the plurality of data extraction sub-modules are provided with the respective portions of the bit stream.

4. The data transporting circuit of claim 1, wherein the data packetizing module comprises a plurality of data packetizing sub-modules, wherein each of the plurality of data packetizing sub-modules is operably coupled output at least a bit per output interval of respective portions of the stored data.

5. The data transporting circuit of claim 4 further comprises a plurality of egress multiplexors operably coupled to the plurality of data packetizing sub-modules, wherein the plurality of egress multiplexors are configurable based on an egress data transport protocol.

6. The data transporting circuit of claim 1, wherein the input interval is synchronized with the output interval.

7. The data transporting circuit of claim 1, wherein the data extraction module comprises ingress local memory for storing the at least a bit of the bit stream per the input interval and for providing the ingress data words to the non-local memory under control of the memory manger, and wherein the data packetizing module comprises egress local memory for storing the egress data words from the non-local memory and for reading the egress data words at least of a bit of the bit stream per the output interval under control of the memory manger.

8. The data transporting circuit of claim 1 further comprises at least one output buffer operably coupled to the non-local memory, the ingress local memory, and the egress local memory.

9. The data v circuit of claim 1, wherein the data packetizing protocols comprises High-level Data Link Controller encapsulated formats.

10. The data transporting circuit of claim 1, wherein the data transport protocol comprises at least one of:

an E1 link format, a T1 link format, and channelized link format.

12. The data transporting circuit of claim 1, wherein the data extraction module provides an indication to the memory manger when the data extraction module has an ingress data word available for transporting, and wherein the data packetizing module provides an indication to the memory manger when the data packetizing module has available memory for receiving an egress data word.

17. The method of claim 1 further comprises:

providing an ingress indication when an ingress data word is available for transporting; and

providing an egress indication when local egress memory is available for receiving an egress data word.

11. The data transporting circuit of claim I further comprises being implemented as an integrated circuit.

13. A method for transporting data, the method comprises the steps of:

a) receiving a bit stream of data at a rate of at least a bit per input interval, wherein the bit stream of data corresponds to ingress packetized data having one of a plurality of data packetizing protocols,

b) extracting data from the bit stream of data to produce extracted data;

c) transporting stored data as egress data words from a non-local memory based, at least in part, on content of the egress data words;

d) packetizing the stored data based on a data packetizing protocol of the plurality of data packetizing protocols to produce egress packetized data;

e) outputting the egress packetized data in a serial manner at a rate of at least a bit per output interval;

f) generating time slot synchronizing information based on at least one of a clock signal, an ingress data transport protocol, and an egress data transport protocol, wherein the input interval and the output interval are based on the time slot synchronizing information; and

g) transporting the extracted data as ingress data words to the non-local memory for storage based, at least in part, on content of the ingress data words.

14. The method of claim 13, wherein step (a) further comprises multiplexing the receiving of the bit stream of data based on an ingress data transport protocol such that portions of the bit stream are received in parallel.

15. The method of claim 13, wherein step (e) further comprises multiplexing the outputting of the egress packetized data based on an egress data transport protocol such that portions of the egress packetized data are received in parallel.

16. The method of claim 13 further comprises synchronizing the input interval with the output interval.

18. A data transporting circuit comprises:

a processing module; and

memory operably coupled to the processing module, wherein the memory includes operating instructions that cause the processing module to (a) receive a bit stream of data at a rate of at least a bit per input interval, wherein the bit stream of data corresponds to ingress packetized data having one of a plurality of data packetizing protocols, (b) extract data from the bit stream of data to produce extracted data;

(c) transport stored data as egress data words from a non-local memory based, at least in part, on content of the egress data words;

(d) packetize the stored data based on a data packetizing protocol of the plurality of data packetizing protocols to produce egress packetized data;

(e) output the egress packetized data in a serial manner at a rate of at least a bit per output interval;

(f) generate time slot synchronizing information based on at least one of a clock signal, an ingress data transport protocol, and an egress data transport protocol, wherein the input interval and the output interval are based on the time slot synchronizing information; and

(g) transport the extracted data as ingress data words to the non-local memory for storage based, at least in part, on content of the ingress data words.

19. The data transporting circuit of claim 18, wherein the memory further comprises operating instructions that cause the processing module to multiplex the receiving of the bit stream of data based on an ingress data transport protocol such that portions of the bit stream are received in parallel.

20. The data transporting circuit of claim 18, wherein the memory further comprises operating instructions that cause the processing module to multiplex the outputting of the egress packetized data based on an egress data transport protocol such that portions of the egress packetized data are received in parallel.

21. The data transporting circuit of claim 18, wherein the memory further comprises operating instructions that cause the processing module to synchronize the input interval with the output interval.

22. The data transporting circuit of claim 18, wherein the memory further comprises operating instructions that cause the processing module to:

provide an ingress indication when an ingress data word is available for transporting; and

provide an egress indication when local egress memory is available for receiving an egress data word.