Booster circuit and semiconductor memory device having the same

• US 6,195,307 B1
• Filed: 02/11/2000
• Issued: 02/27/2001
• Est. Priority Date: 02/26/1997
• Status: Expired due to Term

• Current Assignee: Toshiba Memory Corporation (Kioxia Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Umezawa, Akira, Atsumi, Shigeru, Banba, Hironori
• Primary Examiner(s): Elms, Richard
• Assistant Examiner(s): NGUYEN, VAN THU T
• Application Number:
  US09/502,045
• Time in Patent Office: 382 Days
• Field of Search: 365/226, 365/189.11, 327/536, 327/537
• US Class Current: 365/226
• CPC Class Codes: G11C 16/30 Power supply circuits
• CPC Class Codes: G11C 5/145 Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor G11C5/141 takes precedence

Abstract

In a booster circuit, a gate of an input-side transistor whose end is supplied with a power supply voltage is supplied with an inverted signal of a signal supplied to a signal input terminal of a booster unit at a first stage or supplied with an AND signal of the inverted signal and a booster circuit activation signal. Therefore, when the transistor at the first stage operates, the input-side transistor is turned off. Accordingly, a back flow of a current from inside the booster circuit to a power supply is prevented, so that the efficiency of the booster circuit can be improved. Further, fluctuations of the output voltage are not brought about even when the power supply voltage greatly fluctuates, so that the reliability of peripheral elements and memory cells can be improved and the allowable range of an external power supply voltage can be widened.

Claims

1. A semiconductor device comprising:

a booster circuit having an input terminal, an output terminal, an n-number of transistors composed of a first, a second, . . . , an n-th (where n is a positive integer) transistors diode-connected, and an n-number of capacitors composed of a first, a second, . . . , a n-th capacitors, said n-number of transistors being serially connected between said input terminal and said output terminal, said first transistor being connected to said input terminal and said n-th transistor being connected to said output terminal, each of said n-number of capacitors having a first and a second electrodes, said first electrodes of said n-number of capacitors being respectively connected to gate electrodes of said n-number of transistors, the second electrodes of odd-numbered capacitors among said n-number of capacitors being supplied with a control signal, the second electrodes of even-numbered capacitors among said n-number of capacitors being supplied with a complementary signal of said control signal;

a terminal to which a power supply voltage is supplied;

a charge transfer transistor having a current path and a gate terminal, an end of said current path being connected to said input terminal of said booster circuit, another end of said current path being connected to said terminal, said gate terminal being supplied with said complementary signal of said control signal;

a differential amplifier circuit having a first and a second input terminals and an output terminal, said first input terminal being supplied with a voltage according to a potential of said output terminal of said booster circuit, said second input terminal being supplied with a reference voltage, said output terminal of said differential amplifier circuit outputting an output signal; and

a circuit which is connected to said output terminal of said differential amplifier circuit and produces the control signal and the complimentary signal thereof to be supplied to said booster circuit and said charge transfer transistor.

2. The semiconductor device according to claim 1, wherein said charge transfer transistor is turned off when said first transistor of said first booster circuit operates.

3. The semiconductor device according to claim 1, wherein each of said n-number of transistors is a MOS transistor.

4. The semiconductor device according to claim 1, wherein each of said n-number of transistors is an n-type MOS transistor.

5. The semiconductor device according to claim 1, wherein each of said n-number of transistors is an intrinsic type MOS transistor.

6. The semiconductor device according to claim 1, wherein said charge transfer transistor is a MOS transistor.

7. The semiconductor device according to claim 1, wherein said charge transfer transistor is an n-type MOS transistor.

8. The semiconductor device according to claim 1, wherein said charge transfer transistor is an intrinsic type MOS transistor.

9. A semiconductor device comprising:

a booster circuit having an input terminal, an output terminal, an n-number of transistors composed of a first, a second, . . . , a n-th (where n is a positive integer) transistors diode-connected, and an n-number of capacitors composed of a first, a second, . . . , an n-th capacitors, said n-number of transistors being serially connected between said input terminal and said output terminal, said first transistor being connected to said input terminal and said n-th transistor being connected to said output terminal, each of said n-number of capacitors having a first and a second electrodes, said first electrodes of said n-number of capacitors being respectively connected to gate electrodes of said n-number of transistors, the second electrodes of odd-numbered capacitors among said n-number of capacitors being supplied with a control signal, the second electrodes of even-numbered capacitors among said n-number of capacitors being supplied with a complementary signal of said control signal;

a terminal to which a power supply voltage is supplied;

a charge transfer transistor having a current path and a gate terminal, an end of said current path being connected to said input terminal of said booster circuit, another end of said current path being connected to said terminal, said gate terminal being supplied with a signal based on said complementary signal of said control signal;

a differential amplifier circuit having a first and a second input terminals and an output terminal, said first input terminal being supplied with a voltage according to a potential of said output terminal of said booster circuit, said second input terminal being supplied with a reference voltage, said output terminal of said differential amplifier circuit outputting an output signal; and

a circuit which is connected to said output terminal of said differential amplifier circuit and produces the control signal and the complimentary signal thereof to be supplied to said booster circuit and said charge transfer transistor.

10. The semiconductor device according to claim 9, wherein said signal based on said complementary signal of said control signal is an AND signal of a booster circuit activation signal and said complementary signal.

11. The semiconductor device according to claim 9, wherein said charge transfer transistor is turned off when said first transistor of said first booster circuit operates.

12. The semiconductor device according to claim 9, wherein each of said n-number of transistors is a MOS transistor.

13. The semiconductor device according to claim 9, wherein each of said n-number of transistors is an n-type MOS transistor.

14. The semiconductor device according to claim 9, wherein each of said n-number of transistors is an intrinsic type MOS transistor.

15. The semiconductor device according to claim 9, wherein said charge transfer transistor is a MOS transistor.

16. The semiconductor device according to claim 9, wherein said charge transfer transistor is an n-type MOS transistor.

17. The semiconductor device according to claim 9, wherein said charge transfer transistor is an intrinsic type MOS transistor.