Frequency doubler and method of doubling frequency

• US 6,198,332 B1
• Filed: 09/22/1998
• Issued: 03/06/2001
• Est. Priority Date: 05/13/1996
• Status: Expired due to Term

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Ovard, David K., Tuttle, John R., Rotzoll, Robert R., Tuttle, Mark E., Lowrey, Tyler, Higgins, Brian P., Yu, Shu-Sun, Devereaux, Kevin M., Pax, George E., OʼToole, James E.
• Primary Examiner(s): LAM, TUAN THIEU
• Application Number:
  US09/158,530
• Time in Patent Office: 896 Days
• Field of Search: 327/355, 327/356, 327/357, 327/359, 327/116, 327/119, 327/122
• US Class Current: 327/356
• CPC Class Codes: G06K 19/0707 the arrangement being capable of collecting energy from external energy sources, e.g. thermocouples, vibration, electromagnetic radiation G06K19/0702 takes precedence
• CPC Class Codes: G06K 19/0712 the arrangement being capable of triggering distinct operating modes or functions dependent on the strength of an energy or interrogation field in the proximity of the record carrier active means for hindering electromagnetic reading or writing G06K19/07336
• CPC Class Codes: G06K 19/0716 at least one of the integrated circuit chips comprising a sensor or an interface to a sensor
• CPC Class Codes: G06K 19/0723 the record carrier comprising an arrangement for non-contact communication, e.g. wireless communication circuits on transponder cards, non-contact smart cards or RFIDs
• CPC Class Codes: G06K 19/0726 the arrangement including a circuit for tuning the resonance frequency of an antenna on the record carrier
• CPC Class Codes: G06K 19/07749 the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card
• CPC Class Codes: G06K 19/07758 arrangements for adhering the record carrier to further objects or living beings, functioning as an identification tag
• CPC Class Codes: G06K 7/0008 General problems related to the reading of electronic memory record carriers, independent of its reading method, e.g. power transfer
• CPC Class Codes: G06K 7/10059 transponder driven
• CPC Class Codes: H01Q 1/2225 used in active tags, i.e. provided with its own power source or in passive tags, i.e. deriving power from RF signal
• CPC Class Codes: H03L 7/0995 the oscillator comprising a ring oscillator
• CPC Class Codes: H03L 7/148 said digital means comprising a counter or a divider

Abstract

A frequency doubler includes a first Gilbert cell, a second Gilbert cell coupled to the first Gilbert cell, a frequency generator configured to apply a first sinusoidal wave to the first Gilbert cell, and a phase shifter applying a sinusoidal wave shifted from the first sinusoidal wave to the second Gilbert cell. A method of doubling frequency without using a feedback loop includes providing a first Gilbert cell, providing a second Gilbert cell coupled to the first Gilbert cell, applying a first sinusoidal wave to the first Gilbert cell, and applying a sinusoidal wave shifted from the first sinusoidal wave to the second Gilbert cell.

Claims

1. A frequency doubler comprising:

a first Gilbert cell including a first pair of transistors having sources that are connected together, a second pair of transistors having sources that are connected together, a first one of the transistors of the first pair having a gate defining a first input node and a first one of the transistors of the second pair having a gate connected to the first input node, a second one of the transistors of the first pair having a gate defining a second input node and a second one of the transistors of the second pair having a gate connected to the second input node, the first transistor of the first pair having a drain, and the second transistor of the second pair having a drain connected to the drain of the first transistor of the first pair, the second transistor of the first pair having a drain, and the first transistor of the second pair having a drain connected to the drain of the second transistor of the first pair, a third pair including first and second transistors having sources coupled together, the first transistor of the third pair having a drain connected to the source of the second transistor of the first pair, the second transistor of the third pair having a drain connected to the source of the second transistor of the second pair, and a current source connected to the sources of the third pair and forward biasing the third pair, the second transistor of the third pair having a gate defining a third input node, and the first transistor of the third pair having a gate defining a fourth input node; and

a second Gilbert cell including a first pair of transistors having sources that are connected together, a second pair of transistors having sources that are connected together, a first one of the transistors of the first pair of the second cell having a gate defining a first input node and a first one of the transistors of the second pair of the second cell having a gate connected to the first input node of the second cell, a second one of the transistors of the first pair of the second cell having a gate defining a second input node of the second cell and a second one of the transistors of the second pair of the second cell having a gate connected to the second input node of the second cell, the first transistor of the first pair of the second cell having a drain, and the second transistor of the second pair of the second cell having a drain connected to the drain of the first transistor of the first pair of the second cell, the second transistor of the first pair of the second cell having a drain, and the first transistor of the second pair of the second cell having a drain connected to the drain of the second transistor of the first pair of the second cell, a third pair including first and second transistors having sources coupled together, the first transistor of the third pair of the second cell having a drain connected to the source of the second transistor of the first pair of the second cell, the second transistor of the third pair of the second cell having a drain connected to the source of the second transistor of the second pair of the second cell, and a current source connected to the sources of the third pair of the second cell and forward biasing the third pair of the second cell, the second transistor of the third pair of the second cell having a gate defining a third input node of the second cell, and the first transistor of the third pair of the second cell having a gate defining a fourth input node of the second cell;

the drain of the second transistor of the first pair of the second cell being connected to the drain of the second transistor of the first pair of the first cell, the drain of the second transistor of the second pair of the second cell being connected to the drain of the second transistor of the second pair of the first cell, the first input node of the second cell being connected to the fourth input node of the first cell, the third input node of the second cell being connected to the second input node of the first cell, and the fourth input node of the second cell being connected to the first input node of the first cell.

2. A frequency doubler comprising:

a first Gilbert cell including a first pair of transistors having sources that are coupled together, a second pair of transistors having sources that are coupled together, a first one of the transistors of the first pair having a gate defining a first input node and a first one of the transistors of the second pair having a gate coupled to the first input node, a second one of the transistors of the first pair having a gate defining a second input node and a second one of the transistors of the second pair having a gate coupled to the second input node, the first transistor of the first pair having a drain, and the second transistor of the second pair having a drain coupled to the drain of the first transistor of the first pair, the second transistor of the first pair having a drain, and the first transistor of the second pair having a drain coupled to the drain of the second transistor of the first pair, a third pair including first and second transistors having sources coupled together, the first transistor of the third pair having a drain coupled to the source of the second transistor of the first pair, the second transistor of the third pair having a drain coupled to the source of the second transistor of the second pair, and a current source coupled to the sources of the third pair and forward biasing the third pair, the second transistor of the third pair having a gate defining a third input node, and the first transistor of the third pair having a gate defining a fourth input node; and

a second Gilbert cell including a first pair of transistors having sources that are coupled together, a second pair of transistors having sources that are coupled together, a first one of the transistors of the first pair of the second cell having a gate defining a first input node and a first one of the transistors of the second pair of the second cell having a gate coupled to the first input node of the second cell, a second one of the transistors of the first pair of the second cell having a gate defining a second input node of the second cell and a second one of the transistors of the second pair of the second cell having a gate coupled to the second input node of the second cell, the first transistor of the first pair of the second cell having a drain, and the second transistor of the second pair of the second cell having a drain coupled to the drain of the first transistor of the first pair of the second cell, the second transistor of the first pair of the second cell having a drain, and the first transistor of the second pair of the second cell having a drain coupled to the drain of the second transistor of the first pair of the second cell, a third pair including first and second transistors having sources coupled together, the first transistor of the third pair of the second cell having a drain coupled to the source of the second transistor of the first pair of the second cell, the second transistor of the third pair of the second cell having a drain coupled to the source of the second transistor of the second pair of the second cell, and a current source coupled to the sources of the third pair of the second cell and forward biasing the third pair of the second cell, the second transistor of the third pair of the second cell having a gate defining a third input node of the second cell, and the first transistor of the third pair of the second cell having a gate defining a fourth input node of the second cell;

the drain of the second transistor of the first pair of the second cell being coupled to the drain of the second transistor of the first pair of the first cell, the drain of the second transistor of the second pair of the second cell being coupled to the drain of the second transistor of the second pair of the first cell, the first input node of the second cell being coupled to the fourth input node of the first cell, the third input node of the second cell being coupled to the second input node of the first cell, and the fourth input node of the second cell being coupled to the first input node of the first cell.

3. A method of doubling frequency, the method comprising:

coupling first and second Gilbert cells together, the first Gilbert cell including a first Gilbert cell including a first pair of transistors having sources that are coupled together, a second pair of transistors having sources that are coupled together, a first one of the transistors of the first pair having a gate defining a first input node and a first one of the transistors of the second pair having a gate coupled to the first input node, a second one of the transistors of the first pair having a gate defining a second input node and a second one of the transistors of the second pair having a gate coupled to the second input node, the first transistor of the first pair having a drain, and the second transistor of the second pair having a drain coupled to the drain of the first transistor of the first pair, the second transistor of the first pair having a drain, and the first transistor of the second pair having a drain coupled to the drain of the second transistor of the first pair, a third pair including first and second transistors having sources coupled together, the first transistor of the third pair having a drain coupled to the source of the second transistor of the first pair, the second transistor of the third pair having a drain coupled to the source of the second transistor of the second pair, and a current source coupled to the sources of the third pair and forward biasing the third pair, the second transistor of the third pair having a gate defining a third input node, and the first transistor of the third pair having a gate defining a fourth input node; and

the second Gilbert cell including a first pair of transistors having sources that are coupled together, a second pair of transistors having sources that are coupled together, a first one of the transistors of the first pair of the second cell having a gate defining a first input node and a first one of the transistors of the second pair of the second cell having a gate coupled to the first input node of the second cell, a second one of the transistors of the first pair of the second cell having a gate defining a second input node of the second cell and a second one of the transistors of the second pair of the second cell having a gate coupled to the second input node of the second cell, the first transistor of the first pair of the second cell having a drain, and the second transistor of the second pair of the second cell having a drain coupled to the drain of the first transistor of the first pair of the second cell, the second transistor of the first pair of the second cell having a drain, and the first transistor of the second pair of the second cell having a drain coupled to the drain of the second transistor of the first pair of the second cell, a third pair including first and second transistors having sources coupled together, the first transistor of the third pair of the second cell having a drain coupled to the source of the second transistor of the first pair of the second cell, the second transistor of the third pair of the second cell having a drain coupled to the source of the second transistor of the second pair of the second cell, and a current source coupled to the sources of the third pair of the second cell and forward biasing the third pair of the second cell, the second transistor of the third pair of the second cell having a gate defining a third input node of the second cell, and the first transistor of the third pair of the second cell having a gate defining a fourth input node of the second cell;

the drain of the second transistor of the first pair of the second cell being coupled to the drain of the second transistor of the first pair of the first cell, the drain of the second transistor of the second pair of the second cell being coupled to the drain of the second transistor of the second pair of the first cell, the first input node of the second cell being coupled to the fourth input node of the first cell, the third input node of the second cell being coupled to the second input node of the first cell, and the fourth input node of the second cell being coupled to the first input node of the first cell.

4. A transponder including a frequency multiplier, the frequency multiplier comprising:

a first Gilbert cell including a first pair of transistors having sources that are coupled together, a second pair of transistors having sources that are coupled together, a first one of the transistors of the first pair having a gate defining a first input node and a first one of the transistors of the second pair having a gate coupled to the first input node, a second one of the transistors of the first pair having a gate defining a second input node and a second one of the transistors of the second pair having a gate coupled to the second input node, the first transistor of the first pair having a drain, and the second transistor of the second pair having a drain coupled to the drain of the first transistor of the first pair, the second transistor of the first pair having a drain, and the first transistor of the second pair having a drain coupled to the drain of the second transistor of the first pair, a third pair including first and second transistors having sources coupled together, the first transistor of the third pair having a drain coupled to the source of the second transistor of the first pair, the second transistor of the third pair having a drain coupled to the source of the second transistor of the second pair, and a current source coupled to the sources of the third pair and forward biasing the third pair, the second transistor of the third pair having a gate defining a third input node, and the first transistor of the third pair having a gate defining a fourth input node; and

a second Gilbert cell including a first pair of transistors having sources that are coupled together, a second pair of transistors having sources that are coupled together, a first one of the transistors of the first pair of the second cell having a gate defining a first input node and a first one of the transistors of the second pair of the second cell having a gate coupled to the first input node of the second cell, a second one of the transistors of the first pair of the second cell having a gate defining a second input node of the second cell and a second one of the transistors of the second pair of the second cell having a gate coupled to the second input node of the second cell, the first transistor of the first pair of the second cell having a drain, and the second transistor of the second pair of the second cell having a drain coupled to the drain of the first transistor of the first pair of the second cell, the second transistor of the first pair of the second cell having a drain, and the first transistor of the second pair of the second cell having a drain coupled to the drain of the second transistor of the first pair of the second cell, a third pair including first and second transistors having sources coupled together, the first transistor of the third pair of the second cell having a drain coupled to the source of tile second transistor of the first pair of the second cell, the second transistor of the third pair of the second cell having a drain coupled to the source of the second transistor of the second pair of the second cell, and a current source coupled to the sources of the third pair of the second cell and forward biasing the third pair of the second cell, the second transistor of the third pair of the second cell having a gate defining a third input node of the second cell, and the first transistor of the third pair of the second cell having a gate defining a fourth input node of the second cell;

the drain of the second transistor of the first pair of the second cell being coupled to the drain of the second transistor of the first pair of the first cell, the drain of the second transistor of the second pair of the second cell being coupled to the drain of the second transistor of the second pair of the first cell, the first input node of the second cell being coupled to the fourth input node of the first cell, the third input node of the second cell being coupled to the second input node of the first cell, and the fourth input node of the second cell being coupled to the first input node of the first cell.