Method of fabricating self-aligned stacked gate flash memory cell

• US 6,200,856 B1
• Filed: 07/28/1998
• Issued: 03/13/2001
• Est. Priority Date: 03/25/1998
• Status: Expired due to Term

• Current Assignee: Winbond Electronics Corporation
• Original Assignee: Winbond Electronics Corporation
• Inventors: Chen, Bin-Shing
• Primary Examiner(s): BOOTH, RICHARD A
• Application Number:
  US09/123,852
• Time in Patent Office: 959 Days
• Field of Search: 438/257-267
• US Class Current: 438/257
• CPC Class Codes: H10B 41/30 characterised by the memory core region

Abstract

A technique for forming an integrated circuit device having a self-aligned gate layer and an overlying stacked gate. The method includes a variety of steps such as providing a substrate (217), which is commonly a silicon wafer. Field isolation regions (201) including a first isolation region and a second isolation region are defined in the semiconductor substrate. A recessed region is defined between the first and second isolation regions. The isolation regions (201) are made using a local oxidation of silicon process, which is commonly called LOCOS, but can be others. A thickness of material (205) such as polysilicon is deposited overlying or on the first isolation region, the second isolation region, and the active region. A step of selectively removing portions of the thickness of material overlying portions of the first isolation region and the second isolation region is performed, where the removing step forms a substantially planar material region in the recessed region. A stacked control gate layer is formed overlying the thickness of material.

Claims

1. A method of forming a semiconductor integrated circuit device, said method comprising:

forming a first isolation structure and a second isolation structure on a semiconductor substrate, said isolation structures having an active region defined in a recessed region between said first isolation structure and said second isolation structure;

forming a control gate layer overlying said active region;

forming a first thickness of material overlying said first isolation structure, said second isolation structure, and said active region, wherein said thickness of material substantially fills said recessed region;

selectively removing portions of said thickness of material overlying portions of said first isolation structure and said second isolation structure leaving a substantially planar material region in said recessed region to define a floating gate, said substantially planar material region being self-aligned into said recessed region;

forming a second thickness of material overlying and contacting said substantially planar material region which defines said floating gate; and

forming a dielectric layer overlying said self aligned material region and said second thickness of material, wherein said thickness of material fills at least 75 percent of said recessed region.

2. A method of forming a semiconductor device, comprising:

forming a first isolation region and a second isolation region on a semiconductor substrate, said isolation regions having an active region defined in a first recessed region between said first isolation region and said second isolation region, wherein said first and second isolation regions each includes an insulating structure;

forming a thickness of material overlying said first isolation region, said second isolation region, and said active region;

selectively removing portions of said thickness of material overlying portions of said first isolation region and said second isolation region, so that said first and second isolation regions are substantially free of said thickness of material;

etching a portion of said insulating structure in each of said first and second isolation regions to define a second recessed region;

forming a dielectric layer overlying said thickness of material; and

forming a control gate layer overlying said dielectric layer.

3. The method of claim 2 wherein said thickness of material is deposited overlying said active region to substantially fill said first recessed region.

4. The method of claim 3 wherein said thickness of material is selectively removed to provide a substantially planar material region in said first recessed region.

5. A method of forming a semiconductor device comprising:

forming a plurality of isolation regions, wherein each of said plurality of isolation regions includes an isolating structure;

forming a plurality of active regions, wherein each active region is defined in a recessed region between two isolation regions;

forming a first conductive material overlying said plurality of isolation regions and said plurality of active regions, wherein said first conductive material substantially fills said recessed regions defining said active regions;

removing said first conductive material overlying said plurality of isolation regions while leaving at least a portion of said first conductive material within each of said recessed regions, so that each of said portions of said first conductive material within each of said recessed regions are isolated from each other;

forming a dielectric layer overlying said active regions;

forming a control gate layer overlying said dielectric layer

etching a portion of each of said isolating structures after said removing step;

forming a second conductive material overlying said etched isolating structures; and

selectively removing said second conductive material overlying said isolating structures, so that a portion of said second conductive material coupled to said first conductive material remains on said isolating structures to form a conductive spacer.

6. The method of claim 5 wherein an upper surface of said portions of said first conductive material left within each of said recessed regions is at higher point than an upper surface of each of said etched isolating structures.

7. A method of forming a non-volatile memory device, comprising:

forming first, second, and third isolation regions having first, second, and third isolating structures, respectively;

defining first and second active regions between said first and second isolation regions and said second and third isolation regions, respectively, wherein said first and second active regions include a first recessed region and a second recessed region, respectively;

forming a floating gate material overlying said isolation regions and said active regions, said floating gate material overlying said isolation regions defines a first portion of said floating gate material and said floating gate material overlying said active regions defines a second portion of said floating gate material;

removing a portion of said floating gate material, wherein said first portion of said floating gate material are substantially removed while leaving at least a portion of said second portion of said conductive material overlying the active regions to define a floating gate;

etching a portion of said isolating structures;

forming a conductive spacer material overlying said etched isolating structures;

selectively removing said conductive spacer material to define a conductive spacer joined to said floating gate;

forming a dielectric layer overlying said floating gate and said conductive spacer; and

forming a control gate material overlying said dielectric layer.

8. The method of claim 7 wherein said floating gate is provided over a tunnel oxide layer and said dielectric layer is an ONO layer, wherein said conductive spacer joined to said floating gate increases gate coupling ratio which is defined as;