Data rate synchronization by frame rate adjustment
First Claim
1. A computer system, comprising:
- a central processing unit (CPU);
a data buffer operably coupled to said CPU, wherein said CPU is configured to read data from said data buffer at a first predetermined clock rate;
a clock controller coupled to said data buffer and configured to monitor levels of data in said data buffer, and to provide a signal indicative of said levels of data;
a video camera operably coupled to said data buffer and configured to generate said data and write said data to said data buffer at a second predetermined clock rate, wherein said video camera in coupled to a clock that includes;
a data clock configured to provide a data clock signal; and
a programmable clock divider coupled to said data clock;
wherein said second predetermined clock rate is generated by programming a value into said programmable clock divider and dividing said data clock by said value; and
wherein said value is programmed responsive to said clock controller determining that said levels of data in said data buffer cross a predetermined threshold, such that said second predetermined clock rate approximates said first predetermined clock rate.
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Accused Products
Abstract
A master isochronous clock structure wherein a frame-rate clock of a plurality of data buses are synchronized to a master clock signal. The master clock signal may be derived from the existing clocks signals within the computer system or from data received from an external source. The master clock signal may also be used by an operating system scheduler to schedule task that generate or consume blocks of isochronous data. In an alternative embodiment, the drift of a device clock signal relative to a master clock signal is measured and used to synchronize the device clock signal. For example, a mechanism may monitor the level of data in a data buffer. The level of data in the data buffer is a measure of the drift between the clock generating the data and the clock consuming the data. Based upon the level of data in the buffer, synchronization information is provided to synchronize the rates of the clock signals that generate and consume the data. In one embodiment, the level of data in a data buffer is used to synchronize the clock of a video camera. In another embodiment, the level of data in a data buffer is used to synchronize a clock of a telephony codec.
45 Citations
16 Claims
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1. A computer system, comprising:
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a central processing unit (CPU);
a data buffer operably coupled to said CPU, wherein said CPU is configured to read data from said data buffer at a first predetermined clock rate;
a clock controller coupled to said data buffer and configured to monitor levels of data in said data buffer, and to provide a signal indicative of said levels of data;
a video camera operably coupled to said data buffer and configured to generate said data and write said data to said data buffer at a second predetermined clock rate, wherein said video camera in coupled to a clock that includes;
a data clock configured to provide a data clock signal; and
a programmable clock divider coupled to said data clock;
wherein said second predetermined clock rate is generated by programming a value into said programmable clock divider and dividing said data clock by said value; and
wherein said value is programmed responsive to said clock controller determining that said levels of data in said data buffer cross a predetermined threshold, such that said second predetermined clock rate approximates said first predetermined clock rate. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A computer system, comprising:
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a central processing unit (CPU);
a data buffer operably coupled to said CPU, wherein said CPU is configured to read data from said data buffer at a first predetermined clock rate;
a clock controller coupled to said data buffer and configured to monitor levels of data in said data buffer, and to provide a signal indicative of said levels of data;
a telephony codec operably coupled to said data buffer;
a telephony device operably coupled to said telephony codec, wherein said telephony device is configured to generate said data and said telephony codec is configured to write said data to said data buffer at a second predetermined clock rate, wherein said telephony codec includes;
a data clock configured to provide a data clock signal; and
a programmable clock divider coupled to said data clock;
wherein said second predetermined clock rate is generated by programming a value into said programmable clock divider and dividing said data clock by said value; and
wherein said value is programmed responsive to said clock controller determining that said levels of data in said data buffer cross a predetermined threshold, such that said second predetermined clock rate approximates said first predetermined clock rate. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16)
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Specification