System and method for electrically isolating a device from higher voltage devices

• US 6,205,500 B1
• Filed: 09/24/1997
• Issued: 03/20/2001
• Est. Priority Date: 09/24/1997
• Status: Expired due to Term

• Current Assignee: Hewlett Packard Enterprise Development LP (Hewlett-Packard Enterprise Company)
• Original Assignee: Compaq Computer Corporation (HP Inc.)
• Inventors: Sabotta, Michael L., Grieff, Thomas W.
• Primary Examiner(s): Sheikh, Ayaz R.
• Assistant Examiner(s): JEAN, FRANTZ B
• Application Number:
  US08/936,208
• Time in Patent Office: 1,273 Days
• Field of Search: 395/280, 365/185.11, 365/185.33, 365/189.05, 365/226, 364/784.02, 364/784.03, 710/101, 710/102, 710/104, 710/107, 710/131, 307/75, 307/98, 714/14, 257/355
• US Class Current: 710/100
• CPC Class Codes: G06F 13/4068 Electrical coupling

Abstract

An isolation system and method that electrically couples a device to a bus during cycles associated with or accessing the device, but otherwise isolates the device from the bus. The isolation system includes an isolation device coupled to the device and to the bus that includes an enable input adapted to receive an enable signal, where the isolation device electrically couples the device to said bus while the enable signal is asserted, but otherwise electrically isolates the device from the bus. The isolation system further includes enable logic that detects cycles on the bus and provides the enable signal to the enable input of the isolation device during a cycle if the cycle is associated with the device. The isolation device may comprise a bus switch, one or more discrete isolating devices such as bipolar transistors, field-effect transistors, or any other suitable device for isolating a device from the bus. Generally, the enable logic may comprise decode logic that decodes an address on the bus during the bus cycle to determine if the address corresponds to an address of the device. Decode logic is usefuil for decoding a memory cycle on the bus for accessing a low voltage memory device, which is otherwise isolated from the bus.

Claims

1. An isolation system, comprising:

a first device that is operable at a first voltage level;

a bus that is operable to performs cycles at the first voltage level and a second voltage level;

an isolation device coupled to said first device and to said bus that includes an enable input adapted to receive an enable signal, wherein said isolation device electrically couples said first device to said bus while said enable signal is asserted and the bus operates at the first voltage level, but otherwise electrically isolates said first device from said bus while said enable signal is not asserted and the bus operates at the second voltage level; and

enable logic coupled to said bus that detects cycles on said bus, wherein said enable logic provides said enable signal to said enable input during a bus cycle if said bus cycle corresponds to said first device.

2. The isolation system of claim 1, wherein said isolation device comprises a bus switch.

3. The isolation system of claim 1, further comprising a processor coupled to said bus that executes at least one cycle on said bus to access said first device.

4. The isolation system of claim 1, wherein said isolation device is placed in a high impedance state to electrically isolate said first device from said bus.

5. The isolation system of claim 1, wherein said isolation device comprises at least one field effect transistor (FET).

6. The isolation system of claim 5, wherein said at least one FET comprises a plurality of FETs having a first set of contacts coupled to signal lines of said bus and a second set of contacts coupled to corresponding contacts of said first device and wherein each of said plurality of FETs has a control input controlled by said enable signal.

7. The isolation system of claim 1, further comprising:

a processor coupled to said bus that executes bus cycles and asserts at least one address corresponding to said first device to access said first device.

8. The isolation system of claim 7, wherein said processor and said first device operate according to a logic standard based on approximately three volts.

9. The isolation system of claim 1, further comprising at least one device coupled to said bus that operates at a higher voltage than the maximum operating voltage of said first device.

10. A memory isolation system, comprising:

a bus;

a processor coupled to said bus;

a memory device;

a switching device coupled to said bus and to said memory device and having an enable input that receives an enable signal, wherein said switching device electrically isolates said memory device from said bus while said enable signal is not asserted and electrically couples said memory device to said bus while said enable signal is asserted;

decode logic coupled to said bus that detects a memory cycle on said bus and that correspondingly asserts said enable signal during said memory cycle;

the bus operates at a first voltage level when the memory device and the bus are electrically coupled; and

the bus is operates at a second voltage level when the memory device and the bus are electrically isolated.

11. The memory isolation system of claim 10, further comprising:

said memory device having a set of signal contacts; and

said switching device including a first set of contacts coupled to signal lines of said bus and a second set of contacts coupled to said signal contacts of said memory device.

12. The memory isolation system of claim 11, wherein said switching device comprises a plurality of field effect transistors (FETs), each having first and second controlled terminals forming said first and second contacts, respectively, and each having a control input that receives said enable signal.

13. The memory isolation system of claim 10, wherein said memory device and said processor each operate in accordance with a logic standard based on approximately three volts.

14. The memory isolation system of claim 10, further comprising at least one device coupled to said bus that operates at a higher voltage level than the maximum operating voltage of said memory device.

15. The computer system of claim 10, wherein said switching device is placed in a high impedance state while said enable signal is not asserted to electrically isolate said memory device from said bus.

16. The computer system of claim 10, further comprising:

said memory device having a predetermined range of addresses;

said processor asserting an address on said bus within said predetermined range of addresses during a memory cycle to access said memory device; and

said decode logic further decoding said address asserted on said bus to determrine if said address is within said predetermined range of addresses.

17. A method of electrically coupling an electronic device to a bus while the device is being accessed but otherwise electrically isolating the device from the bus, comprising steps of:

electrically isolating the electronic device from the bus, the electronic device is operable at a first voltage level, the bus is operable to performs cycles at the first voltage level and a second voltage level;

detecting a cycle on the bus associated with the electronic device; and

electrically coupling the electronic device to the bus during the cycle if the cycle is associated with the electronic device and the bus performs the cycle at the first voltage level.

18. The method of claim 17, further comprising a step of a processing device asserting an address on the bus to access the electronic device.

19. The method of claim 17, wherein said step of electrically isolating comprises the steps of:

providing a switching device between the signal contact of the electronic device and corresponding bus signal lines of the bus;

placing the switching device in a high impedent state bearing normal operation to isolate the electronic device from the bus; and

placing the switching device in a closed state to electrically couple the electronic device to the bus during a cycle associated with the electronic device.

20. The method of claim 17, further comprising a step of:

isolating any devices coupled to the bus and operating at a higher voltage than the maximum operating voltage of the electronic device from the bus during cycles associated with the electronic device.