Method for fabricating asymmetric virtual ground P-channel flash cell

• US 6,211,011 B1
• Filed: 07/20/1998
• Issued: 04/03/2001
• Est. Priority Date: 03/05/1997
• Status: Expired due to Term

• Current Assignee: Macronix International Co., Ltd.
• Original Assignee: Macronix International Co., Ltd.
• Inventors: Chen, Chia-Shing
• Primary Examiner(s): TRINH, MICHAEL MANH
• Application Number:
  US09/119,350
• Time in Patent Office: 988 Days
• Field of Search: 438/257, 438/262, 438/263, 438/264, 438/266, 438/258, 438/211, 438/587, 438/588, 438/593, 438/594, 438/525, 257/314
• US Class Current: 438/257
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 16/3427 Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
• CPC Class Codes: H01L 29/7885 Hot carrier injection from the channel
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A memory cell having an asymmetric source and drain connection to virtual ground bit-lines providing an abrupt junction suitable for band-to-band hot electron generation and a gradual junction suitable for Fowler-Nordheim tunneling on each side of the cells. A nonvolatile semiconductor memory device comprising row and column arrangement of the cells in which adjacent columns of cells share a single virtual ground bit line. The method for manufacturing a memory cell having asymmetric source and drain regions and comprising the steps of: (1) forming a semiconductor substrate having a first conductivity type; (3) forming a dielectric covering a semiconductor substrate; (3) forming a first and second column of floating gate cores on the dielectric; (4) implanting a first dopant along a first dopant strip, the first dopant strip aligned between the first and second column and having a second conductivity type opposite the first conductivity type; (5) implanting a second dopant in a second dopant strip aligned with the first diffusion and extending below the second column, the second dopant having an enhancement of the first conductivity type; and (6) completing formation of control gate dielectric and control gates. The presence of asymmetric source and drain diffusions formed thereby improve the isolation between adjacent memory cells and minimizes the disturb problem.

Claims

1. A method for manufacturing asymmetric memory cells in a nonvolatile memory cell array, the method comprising the steps of:

forming a semiconductor substrate characterized by a first conductivity type;

forming a dielectric covering the semiconductor substrate;

forming a first and a second column of floating gate cores on the dielectric;

implanting a first dopant along a first dopant strip, the first dopant strip aligned between the first column and the second column, the first dopant characterized by a second conductivity type;

ion implanting at an angle in a first orientation a second dopant in a second dopant strip, the second dopant strip aligned with the first dopant strip and extending below the second column, the second dopant characterized by being the first conductivity type, and having a higher concentration than said substrate;

ion implanting at an angle in a second orientation a third dopant in a third dopant strip, the third dopant strip aligned with the first dopant strip and extending below the first column, the third dopant characterized by being the second conductivity type, and having a lower concentration than the first dopant strip; and

completing formation of control gate dielectric and control gates.

2. The method for manufacturing an asymmetric memory cell of claim 1, wherein:

said step of implanting the second dopant in the second dopant strip, comprises;

covering the floating gate cores of the first and the second columns with silicon nitride;

patterning a mask over the silicon nitride, to expose the dielectric between the first and the second column;

ion implanting at an angle the second dopant along the second dopant strip; and

removing the patterned mask after the ion implanting.

3. The method for manufacturing an asymmetric memory cell of claim 1, wherein:

said step of implanting the second dopant in the second dopant implant strip and the third dopant in the third dopant strip, comprises;

covering the floating gate cores of the first and the second columns with silicon nitride;

patterning a mask over the silicon nitride, to expose the dielectric between the first column and the second column;

ion implanting at an angle the second dopant along the second dopant strip;

ion implanting at an angle the third dopant along the third dopant strip; and

removing the patterned mask after the ion implanting.

4. A method for manufacturing asymmetric memory cells in a nonvolatile memory cell array, the method comprising the steps of:

implanting an n-type dopant in a semiconductor substrate to provide a well of a first conductivity type;

forming a silicon oxide dielectric over the semiconductor substrate;

forming a first and a second column of floating gate cores on the dielectric over the well;

implanting a p-type dopant along a first dopant strip aligned between the first column and the second column, and having a second conductivity type;

ion implanting at an angle in a first orientation an enhancement of the n-type dopant in a second dopant strip, the second dopant strip aligned with the first dopant strip and extending below the second column, and having a higher conductivity of the first conductivity type than the well;

ion implanting at an angle in a second orientation a diminution of the p-type dopant in a third dopant strip, the third dopant strip aligned with the first dopant strip and extending below the first column, and having a lower conductivity of the second conductivity type than the first dopant strip; and

completing formation of control gate dielectric and control gates.