Semiconductor chip for RF transceiver and power output circuit therefor

• US 6,215,360 B1
• Filed: 02/23/1998
• Issued: 04/10/2001
• Est. Priority Date: 02/23/1998
• Status: Expired due to Term

• Current Assignee: Google Technology Holdings LLC (Alphabet Inc.)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Callaway, Edgar Herbert Jr.
• Primary Examiner(s): Shingleton, Michael B
• Application Number:
  US09/027,783
• Time in Patent Office: 1,142 Days
• Field of Search: 330/286, 330/295, 330/277, 330/250, 330/310, 330/302, 330/307, 252/347, 252/350, 252/352, 252/531, 252/919, 455/73
• US Class Current: 330/310
• CPC Class Codes: H03F 3/607 using FET's

Abstract

A power output circuit is constructed as a distributed amplifier (21) with sufficient stages to make it practical for use as part of a transmitter, while also being integratable as part of a single-chip RF transceiver (72).

Claims

1. An RF power output circuit for developing a desired RF output power Pd, comprising:

a semiconductor material comprising a substrate covered by an insulating layer, and

N topologically equivalent stages of transistors coupled in circuit with passive elements to form a distributed amplifier having an input for receiving an RF signal to be amplified, and having an output, each stage being capable of providing an output power of Q watts,

wherein the distributed amplifier is integrally constructed with the semiconductor material, and wherein the number of stages N of transistors is equal to at least Pd/Q, and wherein each of the N stages is physically separated from the other of the N stages by a distance permitting the RF power output circuit to dissipate heat without damage to the RF power output circuit.

2. An RF power output circuit as set forth in claim 1 wherein the distributed amplifier includes:

a first transmission line having an input for receiving a signal to be amplified;

a second transmission line having an output at which the output power is provided,

and wherein the N stages of transistors are coupled between the first transmission line and the second transmission line.

3. An RF power output circuit as set forth in claim 1 wherein the distributed amplifier includes:

an input transmission line having an input for receiving a signal to be amplified;

an output transmission line having an output at which the output power is provided; and

at least one additional transmission line situated between the input transmission line and the output transmission line,

and wherein stages of transistors are coupled between the input transmission line and the at least one additional transmission line, and between the at least one additional transmission line and the output transmission line.

12. The RF power output circuit according to claim 1, wherein each stage comprises an output transistor that provides approximately 20 milliwatts of power.

13. The RF power output circuit according to claim 1, wherein each stage comprises an output transistor that comprises gate fingers having a total width of approximately 500 microns.

14. The RF power output circuit according to claim 1, wherein each stage comprises an output transistor that provides approximately 20 milliwatts of power.

15. The RF power output circuit according to claim 1, wherein each stage comprises an output transistor that comprises gate fingers having a total width of approximately 500 microns.

4. An RF power output circuit for developing a desired RF output power Pd, comprising:

a semiconductor material comprising a sapphire substrate covered by a layer of silicon; and

N topologically equivalent stages of transistors coupled in circuit with passive elements to form a distributed amplifier having an input for receiving an RF signal to be amplified, and having an output, each stage being capable of providing an output power of Q watts,

wherein the distributed amplifier is integrally constructed with the semiconductor material, and wherein the number of stages N of transistors is equal to at least Pd/Q, and wherein each of the N stages is physically separated from the others of the N stages by a distance permitting the RF power output circuit to dissipate heat without damage to the RF power output circuit.

5. A semiconductor chip for an RF transceiver, comprising:

a semiconductor material comprising a substrate covered by an insulating layer; and

constructed integrally with the semiconductor material;

signal processing circuitry for receiving, amplifying and demodulating incoming RF signals;

a frequency generator for developing at least one signal at a reference frequency for use by the signal processing circuitry;

a power output circuit providing an output signal of a desired transmission power; and

a controller for controlling the operation of the frequency generator, the signal processing circuitry and the power output circuit,

wherein the power output circuit comprises multiple equivalent stages of transistors coupled in circuit with passive elements to form a distributed amplifier, and wherein each of the N stages is physically separated from the other of the N stages by a distance permitting the semiconductor chip to dissipate heat without damage to the semiconductor chip.

6. A semiconductor chip as set forth in claim 5 wherein the substrate is silicon and the insulating layer is silicon dioxide.

7. A semiconductor chip as set forth in claim 6 wherein the number of multiple stages of transistors is selected to be between 16 stages and 32 stages, inclusive.

8. A semiconductor chip as set forth in claim 5 wherein the distributed amplifier includes:

a first transmission line having an input for receiving a signal to be amplified;

a second transmission line having an output at which the output power is provided,

and wherein the multiple stages of transistors are coupled between the first transmission line and the second transmission line.

9. A semiconductor chip as set forth in claim 5 wherein the substrate is silicon and the insulating layer is silicon dioxide.

10. A semiconductor chip as set forth in claim 5 wherein the distributed amplifier includes:

a first transmission line having an input for receiving a signal to be amplified;

a second transmission line; and

a third transmission line having an output at which the output power is provided,

and wherein the multiple stages of transistors are coupled between the first transmission line and the second transmission line, and between the second transmission line and the third transmission line.

16. The semiconductor chip according to claim 5, wherein each stage comprises an output transistor that provides approximately 20 milliwatts of power.

17. The semiconductor chip according to claim 5, wherein each stage comprises an output transistor that comprises gate fingers having a total width of approximately 500 microns.

11. A semiconductor chip for an RF transceiver, comprising:

a semiconductor material comprising a silicon substrate covered by a layer of silicon dioxide; and

constructed integrally with the semiconductor material;

signal processing circuitry for receiving, amplifying and demodulating incoming RF signals;

a frequency generator for developing at least one signal at a reference frequency for use by the signal processing circuitry;

a power output circuit providing an output signal of a desired transmission power; and

a controller for controlling the operation of the frequency generator, the signal processing circuitry and the power output circuit,

wherein the power output circuit comprises an input transmission line, an output transmission line and N equivalent stages of transistors coupled between the input transmission line and the output transmission line, and wherein N is an integer whose value is selected from the range 16-32, depending on the desired level of transmission power, and wherein each of the N stages is physically separated from the other of the N stages by a distance permitting the semiconductor chip to dissipate heat without damage to the semiconductor chip.

18. The semiconductor chip according to claim 11, wherein each stage comprises an output transistor that provides approximately 20 milliwatts of power.

19. The semiconductor chip according to claim 11, wherein each stage comprises an output transistor that comprises gate fingers having a total width of approximately 500 microns.

20. The semiconductor chip according to claim 19, wherein the gate fingers comprise approximately 20 fingers, each being 25 microns wide.

21. A semiconductor chip for an RF transceiver, comprising:

a semiconductor material comprising a substrate covered by an insulating layer; and

constructed integrally with the semiconductor material;

signal processing circuitry for receiving, amplifying and demodulating incoming RF signals;

a frequency generator for developing at least one signal at a reference frequency for use by the signal processing circuitry;

a power output circuit providing an output signal of a desired transmission power; and

a controller for controlling the operation of the frequency generator, the signal processing circuitry and the power output circuit,

wherein the power output circuit comprises N topologically equivalent stages of transistors coupled in circuit with passive elements to form a distributed amplifier, and wherein each of the N stages is physically separated from the other of the N stages by a distance permitting the semiconductor chip to dissipate heat without damage to the semiconductor chip.

22. A semiconductor chip as set forth in claim 21 wherein the substrate is silicon and the insulating layer is silicon dioxide.

23. A semiconductor chip as set forth in claim 22 wherein the number, N, of stages of transistors is selected to be between 16 and 32 inclusive.

24. A semiconductor chip as set forth in claim 21 wherein the distributed amplifier includes:

a first transmission line having an input for receiving a signal to be amplified;

a second transmission line having an output at which the output power is provided,

and wherein the multiple stages of transistors are coupled between the first transmission line and the second transmission line.

25. A semiconductor chip as set forth in claim 21 wherein the substrate is silicon and the insulating layer is silicon dioxide.

26. A semiconductor chip as set forth in claim 21 wherein the distributed amplifier includes:

a first transmission line having an input for receiving a signal to be amplified;

a second transmission line; and

a third transmission line having an output at which the output power is provided,

and wherein the N stages of transistors are coupled between the first transmission line and the second transmission line, and between the second transmission line and the third transmission line.

27. A semiconductor chip for an RF transceiver, comprising:

a semiconductor material comprising a silicon substrate covered by a layer of silicon dioxide; and

constructed integrally with the semiconductor material;

signal processing circuitry for receiving, amplifying and demodulating incoming RF signals;

a frequency generator for developing at least one signal at a reference frequency for use by the signal processing circuitry;

a power output circuit providing an output signal of a desire transmission power, and

a controller for controlling the operation of the frequency generator, the signal processing circuitry and the power output circuit,

wherein the power output circuit comprises an input transmission line, an output transmission line and N topologically equivalent stages of transistors coupled between the input transmission line and the output transmission line, and wherein N is an integer whose value is selected from the range 16-32, depending on the desired level of transmission power, and wherein each of the N stages is physically separated from the other of the N stages by a distance permitting the semiconductor chip to dissipate heat without damage to the semiconductor chip.