Switching circuit device and semiconductor device

• US 6,218,890 B1
• Filed: 07/12/1999
• Issued: 04/17/2001
• Est. Priority Date: 07/14/1998
• Status: Expired due to Fees

• Current Assignee: Sanyo Electric Company Limited (Panasonic Holdings Corporation)
• Original Assignee: Sanyo Electric Company Limited (Panasonic Holdings Corporation)
• Inventors: Sawai, Tetsuro, Yamaguchi, Tsutomu, Uda, Hisanori, Banba, Seiichi
• Primary Examiner(s): Lam, Tuan T.
• Assistant Examiner(s): NGUYEN, LINH M
• Application Number:
  US09/350,924
• Time in Patent Office: 645 Days
• Field of Search: 327/427, 327/431, 327/435, 327/434, 327/436, 333/101, 333/103, 333/104, 333/262
• US Class Current: 327/427
• CPC Class Codes: H01L 27/0605 integrated circuits made of compound material, e.g. AIIIBV
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H03K 17/102 in field-effect transistor switches
• CPC Class Codes: H03K 17/122 in field-effect transistor switches
• CPC Class Codes: H03K 17/6871 the output circuit comprising more than one controlled field-effect transistor

Abstract

A switching circuit device including a multi-gate field effect transistor having a plurality of gate electrodes between a drain electrode and a source electrode, a low resistor having its one end connected between the gate electrodes, and a high resistor connected between the other end of the low resistor and any one of the drain electrode, the source electrode and the end of the other low resistor.

Claims

1. A switching circuit device comprising a multi-gate field effect transistor, wherein

said field effect transistor comprises:

a first ohmic electrode;

a second ohmic electrode;

a plurality of gate electrodes;

a low resistor having its one end connected between the adjacent gate electrodes out of said plurality of gate electrodes; and

a high resistor coupled to said low resistor having a resistance value larger than the resistance value of said low resistor for changing an interstage potential between said adjacent gate electrodes into a predetermined potential through said low resistor.

2. The switching circuit device according to claim 1, wherein

said plurality of gate electrodes comprise a first gate electrode and a second gate electrode adjacent to said first gate electrode,

the one end of said low resistor is connected between said first gate electrode and said second gate electrode, and

said high resistor is connected between the other end of said low resistor and one of said first ohmic electrode and said second ohmic electrode.

3. The switching circuit device according to claim 1, wherein

said plurality of gate electrodes comprise a first gate electrode and a second gate electrode adjacent to said first gate electrode,

said high resistor comprises a first high resistor and a second high resistor,

the one end of said low resistor is connected between said first gate electrode and said second gate electrode,

said first high resistor is connected between the other end of said low resistor and said first ohmic electrode, and

said second high resistor is connected between the other end of said low resistor and said second ohmic electrode.

4. The switching circuit device according to claim 1, wherein

said plurality of gate electrodes comprise a first gate electrode, a second gate electrode adjacent to said first gate electrode, and a third gate electrode adjacent to said second gate electrode,

said low resistor comprises a first low resistor and a second low resistor,

said first low resistor has its one end connected between said first gate electrode and said second gate electrode,

said second low resistor has its one end connected between said second gate electrode and said third gate electrode, and

said high resistor is connected between the other end of said first low resistor and the other end of said second low resistor.

5. The switching circuit device according to claim 1, wherein

said plurality of gate electrodes comprise a first gate electrode, a second gate electrode adjacent to said first gate electrode, and a third gate electrode adjacent to said second gate electrode,

said low resistor comprises a first low resistor and a second low resistor,

said high resistor comprises a first high resistor and a second high resistor,

said first low resistor has its one end connected between said first gate electrode and said second gate electrode,

said second low resistor has its one end connected between said second gate electrode and said third gate electrode,

said first high resistor is connected between the other end of said first low resistor and said first ohmic electrode, and

said second high resistor is connected between the other end of said second low resistor and said second ohmic electrode.

6. The switching circuit device according to claim 1, wherein

said plurality of gate electrodes comprise a first gate electrode, a second gate electrode adjacent to said first gate electrode, and a third gate electrode adjacent to said second gate electrode,

said low resistor comprises a first low resistor and a second low resistor,

said high resistor comprises a first high resistor, a second high resistor, and a third high resistor,

said first low resister has its one end connected between said first gate electrode and said second gate electrode,

said second low resistor has its one end connected between said second gate electrode and said third gate electrode,

said first high resistor is connected between the other end of said first low resistor and said first ohmic electrode,

said second high resistor is connected between the other end of said second low resistor and said second ohmic electrode, and

said third high resistor is connected between the other end of said first low resistor and the other end of said second low resistor.

7. The switching circuit device according to claim 1, wherein

said field effect transistor comprises:

a first field effect transistor connected between a common terminal and a first terminal and receiving a first control signal in the plurality of gate electrodes; and

a second field effect transistor connected between said common terminal and a second terminal and receiving a second control signal which changes so as to be complementary to said first control signal in the plurality of gate electrodes.

8. The switching circuit device according to claim 7, further comprising:

a bias circuit for applying a bias voltage higher than a voltage of said common terminal to said first terminal and said second terminal,

said bias circuit applying said bias voltage to at least one of said first terminal and the low resistor in said first field effect transistor, and applying said bias voltage to at least one of said second terminal and the low resistor in said second field effect transistor.

9. The switching circuit device according to claim 1, wherein

said high resistor is connected to a terminal for bias voltage application.

10. The switching circuit device according to claim 1, wherein

said field effect transistor comprises a plurality of field effect transistors, and

said plurality of field effect transistors are connected in parallel.

11. A semiconductor device comprises:

a semiconductor substrate;

a first ohmic electrode formed on said semiconductor substrate;

a second ohmic electrode formed on said semiconductor substrate;

a first ion implantation area formed in said semiconductor substrate below said first ohmic electrode;

a second ion implantation area formed in said semiconductor substrate below said second ohmic electrode;

an active layer formed in said semiconductor substrate between said first ion implantation area and said second ion implantation area;

a plurality of gate electrodes formed on said active layer;

a low resistance area formed in said semiconductor substrate between the adjacent gate electrodes out of said plurality of gate electrodes; and

a high resistance area formed in said semiconductor substrate beside said active layer and having a resistance value larger than the resistance value of said low resistance area for changing an interstage potential between said adjacent gate electrodes into a predetermined potential through said low resistance area.

12. The semiconductor device according to claim 11, wherein

said plurality of gate electrodes comprise a first gate electrode and a second gate electrode adjacent to the first gate electrode,

said low resistance area is formed between said first gate electrode and said second gate electrode, and

said high resistance area connects said low resistance area to one of said first ion implantation area and said second ion implantation area.

13. The semiconductor device according to claim 11, wherein

said plurality of gate electrodes comprise a first gate electrode and a second gate electrode adjacent to said first gate electrode,

said high resistance area comprises a first high resistance area and a second high resistance area,

said low resistance area is formed between said first gate electrode and said second gate electrode,

said first high resistance area connects said low resistance area and said first ion implantation area, and

said second high resistance area connects said low resistance area and said second ion implantation area.

14. The semiconductor device according to claim 11, wherein

said plurality of gate electrodes comprise a first gate electrode, a second gate electrode adjacent to said first gate electrode, and a third gate electrode adjacent to said second gate electrode,

said low resistance area comprises a first low resistance area and a second low resistance area,

said first low resistance area is formed between said first gate electrode and said second gate electrode,

said second low resistance area is formed between said second gate electrode and said third gate electrode, and

said high resistance area connects said first low resistance area and said second low resistance area.

15. The semiconductor device according to claim 11, wherein

the plurality of gate electrodes comprise a first gate electrode, a second gate electrode adjacent to said first gate electrode, and a third gate electrode adjacent to said second gate electrode,

said low resistance area comprises a first low resistance area and a second low resistance area,

said high resistance area comprises a first high resistance area and a second high resistance area,

said first low resistance area is formed between said first gate electrode and said second gate electrode,

said second low resistance area is formed between said second gate electrode and said third gate electrode,

said first high resistance area connects said first low resistance area and said first ion implantation area, and

said second high resistance area connects said second low resistance area and said second ion implantation area.

16. The semiconductor device according to claim 11, wherein

said plurality of gate electrodes comprise a first gate electrode, a second gate electrode adjacent to said first gate electrode, and a third gate electrode adjacent to said second gate electrode,

said low resistance area comprises a first low resistance area and a second low resistance area,

said high resistance area comprises a first high resistance area, a second high resistance area, and a third high resistance area,

said first low resistance area is formed between said first gate electrode and said second gate electrode,

said second low resistance area is formed between said second gate electrode and said third gate electrode,

said first high resistance area connects said first low resistance area and said first ion implantation area,

said second high resistance area connects said second low resistance area and said second ion implantation area, and

said third high resistance area connects said first low resistance area and said second low resistance area.

17. The semiconductor device according to claim 11, wherein

said high resistance area comprises a plurality of high resistance areas formed between said first and second ohmic electrodes, and

one of the adjacent high resistance areas out of said plurality of high resistance areas is formed on one side of said active layer, and the other high resistance area is formed on the other side of said active layer.

18. The semiconductor device according to claim 17, further comprising:

a plurality of voltage application portions for respectively applying voltages to said plurality of gate electrodes,

one of the adjacent voltage application portions out of said plurality of voltage application portions being formed on one side of said active layer between said high resistance areas, and the other voltage application portion being formed on the other side of said active layer between said high resistance areas.

19. The semiconductor device according to claim 11, wherein

said low resistance area is formed using ion implantation.

20. The semiconductor device according to claim 11, wherein

said high resistance area is formed using ion implantation.