Differential circuits employing forward body bias

• US 6,218,892 B1
• Filed: 02/24/1999
• Issued: 04/17/2001
• Est. Priority Date: 06/20/1997
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Keshavarzi, Ali, Soumyanath, Krishnamurthy, Borkar, Shekhar Y., De, Vivek K.
• Primary Examiner(s): KIM, JUNG H
• Application Number:
  US09/256,842
• Time in Patent Office: 783 Days
• Field of Search: 327/52, 327/65, 327/89, 327/534, 327/537, 327/530
• US Class Current: 327/537
• CPC Class Codes: H01L 27/0928 comprising both N- and P- wells in the substrate, e.g. twin-tub
• CPC Class Codes: H01L 29/1087 characterised by the contact structure of the substrate region, e.g. for controlling or preventing bipolar effect
• CPC Class Codes: H03K 19/0948 using CMOS or complementary insulated gate field-effect transistors
• CPC Class Codes: H03L 7/0816 the controlled phase shifter and the frequency- or phase-detection arrangement being connected to a common input
• CPC Class Codes: H03L 7/0995 the oscillator comprising a ring oscillator

Abstract

In some embodiments, the invention includes circuit having a differential amplifier and body bias control circuitry. The differential amplifier includes a differential pair of first and second FET transistors to at least partially control output voltage signals responsive to input voltage signals, the first and second FET transistors being configured to be matched and having a body. The body bias control circuitry provides a body bias voltage signal to the body to place the first and second FET transistors in a forward body bias condition. The differential amplifier and body bias circuitry may be used in a sense amplifier, comparator, voltage controlled oscillator, delay locked loop, and phase locked loop as well as other circuits.

Claims

1. A circuit comprising:

a differential amplifier including a differential pair of first and second FET transistors to at least partially control output voltage signals responsive to input voltage signals, the first and second FET transistors being configured to be matched and having a body; and

body bias control circuitry to provide a body bias voltage signal to the body to place the first and second FET transistors in a forward body bias condition.

2. The circuit of claim 1, wherein with the forward body bias applied the first and second FET transistors are better matched and an offset voltage of the differential amplifier is reduced as compared to the matching and offset voltage that would exist with a zero body bias.

3. The circuit of claim 1, wherein the differential amplifier further includes a control transistor coupled to the differential pair and wherein the control transistor being is on as a condition to the differential amplifier being operational.

4. The circuit of claim 1, wherein the input conductors include a first input conductor connected to the gate of the first FET transistor and a second input conductor connected to the gate of the second FET transistor.

5. The circuit of claim 1, wherein the input conductors include a first input conductor coupled to the gate of the first FET transistor and a second input conductor coupled to the gate of the second FET transistor.

6. The circuit of claim 5, wherein the input voltage signal includes a Vin+ signal and a Vin−

signal applied to the first and second input conductors, respectively.

7. The circuit of claim 1, wherein the output conductors include a first output conductor connected to the drain of the first FET transistor and a second output conductor connected to the drain of the second FET transistor.

8. The circuit of claim 1, wherein the output conductors include a first output conductor coupled to the drain of the first FET transistor and a second output conductor coupled to the drain of the second FET transistor.

9. The circuit of claim 1, wherein the body bias control circuitry includes a forward body bias mode wherein the body bias voltage signal places the first and second FET transistors in the forward body bias condition and a non-forward body bias mode wherein the body bias voltage signal places the first and second FET transistors in a non-forward body bias condition.

10. The circuit of claim 1, further comprising additional transistors and isolation structure to isolate the first and second FET transistors from at least some of the additional transistors.

11. The circuit of claim 1, wherein the differential amplifier further includes a first load coupled to the drain of the first FET transistor and a second load coupled to the drain of the second FET transistor and wherein the first and second loads are configured to be matched.

12. The circuit of claim 1, wherein the body bias signal is between 400 and 500 millivolts.

13. A circuit comprising:

a differential amplifier in an integrated circuit having a minimum line width Lmin, the differential amplifier including

(a) input conductors to carrying input voltage signals;

(b) output conductors to carrying output voltage signals;

(c) a differential pair of first and second FET transistors coupled to the input and output conductors to receive the input voltage signals and at least partially control the output voltage signals as a function of the input voltage signals, the first and second FET transistors having a body and being configured to be matched, the first and second FET transistors each having a channel length that is between Lmin and 2 Lmin, where Lmin is a minimum line width for the input and output conductors; and

body bias control circuitry to provide a body bias voltage signal to the body to place the first and second FET transistors in a forward body bias condition.

14. The circuit of claim 13, wherein the channel lengths are between Lmin and 1.5 Lmin.

15. The circuit of claim 13, wherein the channel lengths are between Lmin and 1.25 Lmin.

16. A circuit comprising:

a sense amplifier including;

(a) a differential amplifier including a differential pair of first and second FET transistors to at least partially control output voltage signals responsive to input voltage signals on input conductors, the first and second FET transistors being configured to be matched and having a body; and

(b) precharge circuitry coupled to the input conductors; and

body bias control circuitry to provide a body bias voltage signal to the body to place the first and second FET transistors in a forward body bias condition such that the first and second FET transistors are better matched and offset voltage of the differential amplifier is reduced as compared to the matching and offset voltage at zero body bias;

body bias control circuitry to provide a body bias voltage signal to the body to place the first and second FET transistors in a forward body bias condition.

17. The circuit of claim 16, wherein with the forward body bias applied the first and second FET transistors are better matched and an offset voltage of the differential amplifier is reduced as compared to the matching and offset voltage that would exist with a zero body bias.

18. A circuit comprising:

a differential voltage control oscillator including differential amplifier stages each including a differential amplifier including a differential pair of first and second FET transistors to at least partially control output voltage signals responsive to input voltage signals on input conductors, the first and second FET transistors being configured to be matched and the differential pairs having a body; and

body bias control circuitry to provide a body bias voltage signal to the body of at least some of the differential amplifier stages to place the first and second FET transistors of those stages in a forward body bias condition; and

voltage control circuitry to provide a voltage control circuitry to at least some of the differential amplifier stages.

19. The circuit of claim 18, wherein with the forward body bias applied the first and second FET transistors are better matched and an offset voltage of the differential amplifier is reduced as compared to the matching and offset voltage that would exist with a zero body bias.

20. The circuit of claim 18, wherein there are an odd number of differential amplifier stages.

21. The circuit of claim 18, wherein there are an even number of differential amplifier stages.

22. A circuit comprising:

a differential delay locked loop including differential amplifier stages each including a differential amplifier including a differential pair of first and second FET transistors to at least partially control output voltage signals responsive to input voltage signals on input conductors, the first and second FET transistors being configured to be matched and the differential pairs having a body; and

body bias control circuitry to provide a body bias voltage signal to the body of at least some of the differential amplifier stages to place the first and second FET transistors of those stages in a forward body bias condition; and

voltage control circuitry to provide a voltage control circuitry to at least some of the differential amplifier stages.

23. The circuit of claim 22, wherein with the forward body bias applied the first and second FET transistors are better matched and an offset voltage of the differential amplifier is reduced as compared to the matching and offset voltage that would exist with a zero body bias.

24. The circuit of claim 22, wherein there are an odd number of differential amplifier stages.

25. The circuit of claim 22, wherein there are an even number of differential amplifier stages.

26. The circuit of claim 22, further comprising phase detector circuitry having an output and wherein the body bias control is controlled by the output signal.

27. A circuit comprising:

a differential phase locked loop including differential amplifier stages each including a differential amplifier including a differential pair of first and second FET transistors to at least partially control output voltage signals responsive to input voltage signals on input conductors, the first and second FET transistors being configured to be matched and the differential pairs having a body; and

body bias control circuitry to provide a body bias voltage signal to the body of at least some of the differential amplifier stages to place the first and second FET transistors of those stages in a forward body bias condition; and

voltage control circuitry to provide a voltage control circuitry to at least some of the differential amplifier stages.

28. The circuit of claim 27, wherein with the forward body bias applied the first and second FET transistors are better matched and an offset voltage of the differential amplifier is reduced as compared to the matching and offset voltage that would exist with a zero body bias.

29. The circuit of claim 27, wherein there are an even number of differential amplifier stages.

30. The circuit of claim 27, further comprising phase detector circuitry having an output and wherein the body bias control is controlled by the output signal.