Method and apparatus for reducing EMI in a computer system

• US 6,219,255 B1
• Filed: 08/20/1998
• Issued: 04/17/2001
• Est. Priority Date: 08/20/1998
• Status: Expired due to Term

• Current Assignee: Dell USA LP (Dell Technologies Inc.)
• Original Assignee: Dell USA LP (Dell Technologies Inc.)
• Inventors: Teshome, Abeye
• Primary Examiner(s): Gaffin, Jeffrey
• Assistant Examiner(s): Vigushin, John B.
• Application Number:
  US09/137,472
• Time in Patent Office: 971 Days
• Field of Search: 361/748, 361/777, 361/778, 361/780, 361/794, 361/818, 174/250, 174/253, 174/255, 174/261, 333/12, 333/24.R, 333/32, 333/33, 333/99.R, 333/246, 333/247, 257/728, 298/30, 298/31, 298/46
• US Class Current: 361/794
• CPC Class Codes: H05K 1/0216 Reduction of cross-talk, noise or electromagnetic interference grounding H05K1/0215
• CPC Class Codes: H05K 1/0253 Impedance adaptations of transmission lines by special lay-out of power planes, e.g. providing openings H05K1/0251 takes precedence
• CPC Class Codes: H05K 1/0262 Arrangements for regulating voltages or for using plural voltages
• CPC Class Codes: H05K 2201/09245 Crossing layout alternating conductors H05K2201/097
• CPC Class Codes: H05K 2201/093 Layout of power planes, ground planes or power supply conductors, e.g. having special clearance holes therein reduction of cross-talk, noise or interference by patterned shielding planes, ground planes or power planes H05K1/0224
• CPC Class Codes: H05K 2201/09345 Power and ground in the same plane; Power planes for two voltages in one plane
• CPC Class Codes: H05K 2201/09663 Divided layout, i.e. conductors divided in two or more parts branched layout H05K2201/09254
• CPC Class Codes: H05K 2201/09781 Dummy conductors, i.e. not used for normal transport of current; Dummy electrodes of components
• CPC Class Codes: H05K 2201/10689 Leaded Integrated Circuit [IC] package, e.g. dual-in-line [DIL]
• CPC Class Codes: H05K 9/0039 Galvanic coupling of ground layer on printed circuit board [PCB] to conductive casing printed shielding conductors, ground planes or power planes for reduction of cross-talk or noise in printed circuits H05K1/0218
• CPC Class Codes: Y10T 29/49155 Manufacturing circuit on or in base

Abstract

A computer system includes a microprocessor, an an input coupled to provide signal inputs to the microprocessor, a mass storage coupled to the microprocessor, a video controller for coupling the microprocessor to a display, a memory coupled to provide storage to facilitate execution of computer programs by the microprocessor, and a multilayer printed circuit board for mounting the microprocessor thereon. The multilayer printed circuit board provides for reduced electromagnetic interference (EMI) and includes at least two layers. The multilayer printed circuit board further includes a first conductive segment on a first layer, a second conductive segment on the first layer, the second segment being separated from the first segment by a primary gap, and a conductive interconnect on a second layer, the interconnect for carrying a high frequency signal therein. The second layer is disposed laterally from and substantially parallel to the first layer. The interconnect is further disposed for crossing over the first segment to the second segment in a cross-over region and wherein the first segment and the second segment are further characterized by a secondary gap in the cross-over region, the secondary gap being less than the primary gap for providing an increased coupling in the cross-over region. A method for reducing a source of EMI in a multilayer printed circuit board is also disclosed.

Claims

1. A multilayer printed circuit board disposed for reducing a source of electromagnetic interference (EMI) and having at least two layers, said multilayer printed circuit board comprising:

a first conductive segment on a first layer;

a second conductive segment on the first layer, said second segment being separated from said first segment by a primary gap; and

a conductive interconnect on a second layer, said interconnect for carrying a high frequency signal therein, the second layer being disposed laterally from and substantially parallel to the first layer, said interconnect further being disposed for crossing over said first segment to said second segment in a cross-over region and wherein said first segment and said second segment are further characterized by a secondary gap in the cross-over region, the secondary gap being less than the primary gap for providing an increased coupling in the cross-over region.

2. The multilayer printed circuit board of claim 1, wherein in the cross-over region, said first segment and said second segment are further characterized by an interlocking arrangement.

3. The multilayer printed circuit board of claim 2, wherein the interlocking arrangement further includes rectangular shaped mating features, said first segment including a first mating feature and said second segment including a second mating feature, the first and second mating features being spaced apart from one another by a spacing on the order of the secondary gap.

4. The multilayer printed circuit board of claim 3, further comprising at least one floating conductive interconnect on the second layer in addition to said high frequency signal interconnect, said at least one floating interconnect being disposed substantially parallel to said high frequency signal interconnect and for crossing over said first segment to said second segment in the cross-over region.

5. The multilayer printed circuit board of claim 2, wherein the interlocking arrangement further includes circular shaped mating features, said first segment including a first mating feature and said second segment including a second mating feature, the first and second mating features being spaced apart from one another by a spacing on the order of the secondary gap.

6. The multilayer printed circuit board of claim 5, further comprising at least one floating conductive interconnect on the second layer in addition to said high frequency signal interconnect, said at least one floating interconnect being disposed substantially parallel to said high frequency signal interconnect and for crossing over said first segment to said second segment in the cross-over region.

7. The multilayer printed circuit board of claim 2, wherein the interlocking arrangement further includes first and second counterpart features, said first segment including the first counterpart feature and said second segment including the second counterpart feature, the first and second counterpart features being spaced apart from one another by a spacing on the order of less than or equal to the secondary gap.

8. The multilayer printed circuit board of claim 7, further comprising at least one floating conductive interconnect on the second layer in addition to said high frequency signal interconnect, said at least one floating interconnect being disposed substantially parallel to said high frequency signal interconnect and for crossing over said first segment to said second segment in the cross-over region.

9. The multilayer printed circuit board of claim 1, wherein the secondary gap is on the order of ten to seventy-five percent (10-75%) of the primary gap.

10. The multilayer printed circuit board of claim 9, further wherein the secondary gap is on the order of twenty percent (20%) of the primary gap.

11. The multilayer printed circuit board of claim 1, wherein in the cross-over region, said first segment and said second segment are further characterized by a non-interlocking arrangement.

12. The multilayer printed circuit board of claim 11, wherein the non-interlocking arrangement further includes rectangular shaped mating features, said first segment including a first mating feature and said second segment including a second mating feature, the first and second mating features being spaced apart from one another by a spacing on the order of the secondary gap.

13. The multilayer printed circuit board of claim 12, further comprising at least one floating conductive interconnect on the second layer in addition to said high frequency signal interconnect, said at least one floating interconnect being disposed substantially parallel to said high frequency signal interconnect and for crossing over said first segment to said second segment in the cross-over region.

14. The multilayer printed circuit board of claim 11, wherein the non-interlocking arrangement further includes circular shaped mating features, said first segment including a first mating feature and said second segment including a second mating feature, the first and second mating features being spaced apart from one another by a spacing on the order of the secondary gap.

15. The multilayer printed circuit board of claim 14, further comprising at least one floating conductive interconnect on the second layer in addition to said high frequency signal interconnect, said at least one floating interconnect being disposed substantially parallel to said high frequency signal interconnect and for crossing over said first segment to said second segment in the cross-over region.

16. The multilayer printed circuit board of claim 11, wherein the non-interlocking arrangement further includes first and second counterpart features, said first segment including the first counterpart feature and said second segment including the second counterpart feature, the first and second counterpart features being spaced apart from one another by a spacing on the order of less than or equal to the secondary gap.

17. The multilayer printed circuit board of claim 16, further comprising at least one floating conductive interconnect on the second layer in addition to said high frequency signal interconnect, said at least one floating interconnect being disposed substantially parallel to said high frequency signal interconnect and for crossing over said first segment to said second segment in the cross-over region.

18. A computer system comprising:

a microprocessor;

an input coupled to provide signal inputs to said microprocessor;

a mass storage coupled to said microprocessor;

a video controller for coupling said microprocessor to a display;

a memory coupled to provide storage to facilitate execution of computer programs by said microprocessor; and

a multilayer printed circuit board for mounting said microprocessor thereon, said multilayer printed circuit board providing for reduced electromagnetic interference (EMI) and having at least two layers, further including a first conductive segment on a first layer, a second conductive segment on the first layer, the second segment being separated from the first segment by a primary gap, and a conductive interconnect on a second layer, the interconnect for carrying a high frequency signal therein, the second layer being disposed laterally from and substantially parallel to the first layer, the interconnect further being disposed for crossing over the first segment to the second segment in a cross-over region and wherein the first segment and the second segment are further characterized by a secondary gap in the crossover region, the secondary gap being less than the primary gap for providing an increased coupling in the cross-over region.

19. The system of claim 18, wherein in the cross-over region, the first segment and the second segment are further characterized by an interlocking arrangement.

20. The system of claim 19, wherein the interlocking arrangement further includes rectangular shaped mating features, the first segment including a first mating feature and the second segment including a second mating feature, the first and second mating features being spaced apart from one another by a spacing on the order of the secondary gap.

21. The system of claim 20, further comprising at least one floating conductive interconnect on the second layer in addition to the high frequency signal interconnect, the at least one floating interconnect being disposed substantially parallel to the high frequency signal interconnect and for crossing over the first segment to the second segment in the cross-over region.

22. The system of claim 19, wherein the interlocking arrangement further includes circular shaped mating features, the first segment including a first mating feature and the second segment including a second mating feature, the first and second mating features being spaced apart from one another by a spacing on the order of the secondary gap.

23. The system of claim 22, further comprising at least one floating conductive interconnect on the second layer in addition to the high frequency signal interconnect, the at least one floating interconnect being disposed substantially parallel to the high frequency signal interconnect and for crossing over the first segment to the second segment in the cross-over region.

24. The system of claim 19, wherein the interlocking arrangement further includes first and second counterpart features, the first segment including the first counterpart feature and the second segment including the second counterpart feature, the first and second counterpart features being spaced apart from one another by a spacing on the order of less than or equal to the secondary gap.

25. The system of claim 24, further comprising at least one floating conductive interconnect on the second layer in addition to the high frequency signal interconnect, the at least one floating interconnect being disposed substantially parallel to the high frequency signal interconnect and for crossing over the first segment to the second segment in the cross-over region.

26. The system of claim 18, wherein the secondary gap is on the order of ten to seventy-five percent (10-75%) of the primary gap.

27. The system of claim 26, further wherein the secondary gap is on the order of twenty percent (20%) of the primary gap.

28. The system of claim 18, wherein in the cross-over region, the first segment and the second segment are further characterized by a non-interlocking arrangement.

29. The system of claim 28, wherein the non-interlocking arrangement further includes rectangular shaped mating features, the first segment including a first mating feature and the second segment including a second mating feature, the first and second mating features being spaced apart from one another by a spacing on the order of the secondary gap.

30. The system of claim 29, further comprising at least one floating conductive interconnect on the second layer in addition to the high frequency signal interconnect, the at least one floating interconnect being disposed substantially parallel to the high frequency signal interconnect and for crossing over the first segment to the second segment in the cross-over region.

31. The system of claim 28, wherein the non-interlocking arrangement further includes circular shaped mating features, the first segment including a first mating feature and the second segment including a second mating feature, the first and second mating features being spaced apart from one another by a spacing on the order of the secondary gap.

32. The system of claim 31, further comprising at least one floating conductive interconnect on the second layer in addition to the high frequency signal interconnect, the at least one floating interconnect being disposed substantially parallel to the high frequency signal interconnect and for crossing over the first segment to the second segment in the cross-over region.

33. The system of claim 28, wherein the non-interlocking arrangement further includes first and second counterpart features, the first segment including the first counterpart feature and the second segment including the second counterpart feature, the first and second counterpart features being spaced apart from one another by a spacing on the order of less than or equal to the secondary gap.

34. The system of claim 33, further comprising at least one floating conductive interconnect on the second layer in addition to the high frequency signal interconnect, the at least one floating interconnect being disposed substantially parallel to the high frequency signal interconnect and for crossing over the first segment to the second segment in the cross-over region.

35. A method for reducing a source of electromagnetic interference (EMI) in a multilayer printed circuit board, the multilayer printed circuit board having at least two layers, said method comprising the steps of:

providing a first conductive segment on a first layer;

providing a second conductive segment on the first layer, the second segment being separated from the first segment by a primary gap; and

providing a conductive interconnect on a second layer, the interconnect for carrying a high frequency signal therein, the second layer being disposed laterally from and substantially parallel to the first layer, the interconnect further being disposed for crossing over the first segment to the second segment in a cross-over region and wherein the first segment and the second segment are further characterized by a secondary gap in the cross-over region, the secondary gap being less than the primary gap for providing an increased coupling in the cross-over region.

36. The method of claim 35, wherein in the cross-over region, the first segment and the second segment are further characterized by an interlocking arrangement.

37. The method of claim 36, wherein the interlocking arrangement further includes rectangular shaped mating features, the first segment including a first mating feature and the second segment including a second mating feature, the first and second mating features being spaced apart from one another by a spacing on the order of the secondary gap.

38. The method of claim 37, further comprising the step of providing at least one floating conductive interconnect on the second layer in addition to the high frequency signal interconnect, the at least one floating interconnect being disposed substantially parallel to the high frequency signal interconnect and for crossing over the first segment to the second segment in the cross-over region.

39. The method of claim 36, wherein the interlocking arrangement further includes circular shaped mating features, the first segment including a first mating feature and the second segment including a second mating feature, the first and second mating features being spaced apart from one another by a spacing on the order of the secondary gap.

40. The method of claim 39, further comprising the step of providing at least one floating conductive interconnect on the second layer in addition to the high frequency signal interconnect, the at least one floating interconnect being disposed substantially parallel to the high frequency signal interconnect and for crossing over the first segment to the second segment in the cross-over region.

41. The method of claim 36, wherein the interlocking arrangement further includes first and second counterpart features, the first segment including the first counterpart feature and the second segment including the second counterpart feature, the first and second counterpart features being spaced apart from one another by a spacing on the order of less than or equal to the secondary gap.

42. The method of claim 41, further comprising the step of providing at least one floating conductive interconnect on the second layer in addition to the high frequency signal interconnect, the at least one floating interconnect being disposed substantially parallel to the high frequency signal interconnect and for crossing over the first segment to the second segment in the cross-over region.

43. The method of claim 35, wherein the secondary gap is on the order of ten to seventy-five percent (10-75%) of the primary gap.

44. The method of claim 43, further wherein the secondary gap is on the order of twenty percent (20%) of the primary gap.

45. The method of claim 35, wherein in the cross-over region, the first segment and the second segment are further characterized by a non-interlocking arrangement.

46. The method of claim 45, wherein the non-interlocking arrangement further includes rectangular shaped mating features, the first segment including a first mating feature and the second segment including a second mating feature, the first and second mating features being spaced apart from one another by a spacing on the order of the secondary gap.

47. The method of claim 46, further comprising the step of providing at least one floating conductive interconnect on the second layer in addition to the high frequency signal interconnect, the at least one floating interconnect being disposed substantially parallel to the high frequency signal interconnect and for crossing over the first segment to the second segment in the cross-over region.

48. The method of claim 45, wherein the non-interlocking arrangement further includes circular shaped mating features, the first segment including a first mating feature and the second segment including a second mating feature, the first and second mating features being spaced apart from one another by a spacing on the order of the secondary gap.

49. The method of claim 48, further comprising the step of providing at least one floating conductive interconnect on the second layer in addition to the high frequency signal interconnect, the at least one floating interconnect being disposed substantially parallel to the high frequency signal interconnect and for crossing over the first segment to the second segment in the cross-over region.

50. The method of claim 45, wherein the non-interlocking arrangement further includes first and second counterpart features, the first segment including the first counterpart feature and the second segment including the second counterpart feature, the first and second counterpart features being spaced apart from one another by a spacing on the order of less than or equal to the secondary gap.

51. The method of claim 50, further comprising the step of providing at least one floating conductive interconnect on the second layer in addition to the high frequency signal interconnect, the at least one floating interconnect being disposed substantially parallel to the high frequency signal interconnect and for crossing over the first segment to the second segment in the cross-over region.