Fault tolerant memory
First Claim
Patent Images
1. A computer system comprising:
- memory chip units each comprising individual memory chip modules removably connected by respective memory chip module connectors to a memory bus coupled to a memory controller;
a central processing unit; and
said memory controller configured to access the memory chip units in response to interaction with the central processing unit and define a fault tolerant memory array with the memory chip units, each memory chip unit storing first data represented by second data stored by the other memory chip units;
said memory controller operable to;
correct corrupted first data retrieved from a memory chip unit using error correction code associated with the retrieved data and when the retrieved first data from said memory chip unit cannot be corrected by said error correction code, restoring said first data stored in said memory chip unit by replacement with said second data.
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Abstract
A computer system includes memory modules, a central processing unit and a memory controller. The memory controller is configured to access the memory modules in response to interaction with the central processing unit and define a fault tolerant memory array with the memory modules. Each memory module stores first data represented by second data stored by the other memory modules.
294 Citations
16 Claims
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1. A computer system comprising:
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memory chip units each comprising individual memory chip modules removably connected by respective memory chip module connectors to a memory bus coupled to a memory controller;
a central processing unit; and
said memory controller configured to access the memory chip units in response to interaction with the central processing unit and define a fault tolerant memory array with the memory chip units, each memory chip unit storing first data represented by second data stored by the other memory chip units;
said memory controller operable to;
correct corrupted first data retrieved from a memory chip unit using error correction code associated with the retrieved data and when the retrieved first data from said memory chip unit cannot be corrected by said error correction code, restoring said first data stored in said memory chip unit by replacement with said second data. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A computer system comprising:
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at least one processor coupled to a disk storage device and to a fault tolerant redundant memory chip array comprising a plurality of memory chip modules removably connected to a memory bus, said memory chip modules storing stripes of data and parity data associated with respective ones of said stripes of data;
said processor and said redundant memory array coupled to a memory controller operable under control of said processor to write data to and to retrieve data from said redundant memory array;
said memory controller also operable to;
detect errors in corrupted data stored by said memory chip modules in said stripes of data, generate error correction code information associated with the corrupted data, and store the error correction code information in the memory chip module which stores the corrupted data; and
determine whether corrupted data retrieved from a memory module can be corrected using the stored error correction code information associated with that corrupted data;
if so, correcting the corrupted data using the associated error correction code information;
if not, restoring the corrupted data stored by said memory module by replacement with data derived from uncorrupted data in that data stripe and said parity data associated with that data stripe. - View Dependent Claims (12, 13, 14, 15, 16)
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Specification