Detector for electromagnetic radiation, pixel structure with high sensitivity using such detector and method of manufacturing such detector

• US 6,225,670 B1
• Filed: 02/09/1998
• Issued: 05/01/2001
• Est. Priority Date: 06/04/1997
• Status: Expired due to Term

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: IMEC International
• Inventors: Dierickx, Bart
• Primary Examiner(s): WOJCIECHOWICZ, EDWARD JOSEPH
• Application Number:
  US09/021,010
• Time in Patent Office: 1,177 Days
• Field of Search: 257/291, 257/292, 257/431, 257/443, 257/450, 257/461, 257/463
• US Class Current: 257/431
• CPC Class Codes: H01L 27/14601 Structural or functional details thereof
• CPC Class Codes: H01L 27/14643 Photodiode arrays; MOS imagers

Abstract

The present invention discloses a semiconductor based detector for radiation with a small but effective barrier between the radiation sensitive volume in the semiconductor and the regions and junctions with readout circuitry, and with no or a lower barrier between the semiconductor substrate and the regions and junctions adapted and meant for collecting the charge carriers generated by the radiation in the semiconductor substrate.

Claims

1. A detector for electromagnetic radiation including a semiconductor substrate having dopants of a first conductivity type, wherein said substrate comprises a first region and a second region both having dopants of a second conductivity type, said first region and said second region being adapted for collecting charge carriers being generated by radiation in said substrate, said substrate further comprising a third region having dopants of the first conductivity type at a higher doping level than the substrate, the third region forming a barrier for substantially impeding the diffusion of said charge carriers to said second region.

2. A detector as recited in claim 1, wherein said substrate comprises a first region, a second and a third region, said first region and said second region and possibly said third region are exposed to radiation.

3. A detector as recited in claim 1, wherein between the substrate and the first region, there is no barrier present or a substantially zero barrier present or a substantially lower barrier than in between said second region and said substrate.

4. A detector as recited in claim 1, wherein said third region is forming a substantially lower barrier for the diffusion of said charge carriers to said first region.

5. A detector as recited in claim 1 having a small but effective barrier between the radiation sensitive volume in the semiconductor substrate and the regions and junctions with read-out circuitry with no or a lower barrier between the radiation sensitive volume in the semiconductor and the regions and junctions adapted and meant for collecting the charge carriers being generated by the radiation.

6. The detector as recited in claim 1, wherein at least part of the charge carriers that are generated in said substrate underneath said second region are collected by said first region.

7. The detector as recited in claim 6, wherein said first region forms a junction with said substrate and said second region forms a junction with said third region.

8. The detector as recited in claim 7, wherein said first region is part of a phototransistor.

9. The detector as recited in claim 8, wherein said phototransistor is a vertical npn structure or vertical pnp structure, and wherein said substrate is the collector of said phototransistor, said first region is the base of said phototransistor, said first region further comprising a fifth region being the emitter of said phototransistor.

10. The detector as recited in claim 1, further comprising a fourth region adjoining said first region and said substrate, said fourth region having dopants of said second conductivity type.

11. The detector as recited in claim 1, being integrated in a CCD or in a CCD-like sensor and wherein said first region is an inversion layer or a buried channel beneath the electrode of said CCD or said CCD-like sensor.

12. The detector as recited in claim 11, wherein said CCD-like sensor is a photogate or a charge injection device or a charge sweep device.

13. A MOS based pixel structure for detecting light comprising the detector as recited in claim 1, wherein said third region forms an electrostatic barrier for substantially impeding the diffusion of electrons or holes to said second region, said barrier being formed at the interface between said third region and said substrate.

14. The pixel structure as recited in claim 13, wherein in between the substrate and the first region, there is no barrier present or a substantially zero barrier present or a substantially lower barrier than in between said second region and said substrate.

15. The pixel structure as recited in claim 13, said third region is forming a substantially lower barrier for the diffusion of said charge carriers to said first region.

16. The pixel structure as recited in claim 13, wherein a detector having a small but effective barrier between the radiation sensitive volume in the semiconductor substrate and the regions and junctions with read-out circuitry with no or a lower barrier between the radiation sensitive volume in the semiconductor and the regions and junctions adapted and meant for collecting the charge carriers being generated by the radiation.

17. The pixel structure as recited in claim 13, wherein said first region is a depletion layer or an inversion layer of a MOS component or of a buried channel MOS transistor.

18. The pixel structure as recited in claim 13, wherein said second region is part of a circuit for processing the signal being generated by said charge carriers in said first region.

19. The pixel structure as recited in claim 13, wherein said substrate is a p type substrate, said third region being a p type region of a higher doping level, said first and said second region being n type regions.

20. The pixel structure as recited in claim 19, further comprising a fourth region adjoining said first region and said substrate and wherein said fourth region is a n type region.

21. The pixel structure as recited in claim 19 or 20, wherein said first region is the first electrode of a MOS transistor, said first junction being at least partially surrounded by the gate of said MOS transistor, the second electrode surrounding at least partially said gate and said first electrode.

22. The pixel structure as recited in claim 21, wherein said first electrode is the source or the drain of said MOS transistor, said second electrode being the drain or the source of said MOS transistor.

23. The pixel structure as recited in claim 13, wherein said pixel structure further comprises a memory element.

24. The pixel structure as recited in claim 13, wherein said memory element comprises a capacitor, the charge being generated in said first region being stored on said capacitor over a switch, at least a part of said capacitor being shielded from said radiation by a protecting metal layer on top of said pixel structure.

25. A method of operating the pixel structure as recited in claim 22, comprising the step of electrically isolating said first and said second electrode.

26. The method as recited in claim 25, further comprising the step of tying said second electrode to a voltage in a predetermined range, said gate being biased in the “

off”

state.

27. A detector as recited in claim 1, further comprising a metallisation contact, said contact being on said first region.