Method of fabricating field effect transistor

• US 6,228,730 B1
• Filed: 04/28/1999
• Issued: 05/08/2001
• Est. Priority Date: 04/28/1999
• Status: Active Grant

• Current Assignee: United Microelectronics Corporation
• Original Assignee: United Microelectronics Corporation
• Inventors: Chen, Tung-Po, Chou, Jih-Wen
• Primary Examiner(s): Niebling, John F.
• Assistant Examiner(s): LINDSAY JR, WALTER LEE
• Application Number:
  US09/301,211
• Time in Patent Office: 741 Days
• Field of Search: 257/67, 438/361, 438/474, 438/371, 438/507, 438/309, 438/305, 438/586
• US Class Current: 438/301
• CPC Class Codes: H01L 21/28518 the conductive layers comprising silicides H01L21/28537 takes precedence
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/66628 recessing the gate by forming single crystalline semiconductor material at the source or drain location
• CPC Class Codes: H01L 29/7834 with a non-planar structure, e.g. the gate or the source or the drain being non-planar

Abstract

A method of fabricating a field effect transistor, wherein a substrate with a gate is provided. A liner oxide layer and a first spacer are formed adjacent to the sides of the gate. An epitaxial silicon layer is formed at both sides of the gate in the substrate, while a shallow source/drain (S/D) extension junction is formed in the substrate below the epitaxial silicon layer. An oxide layer and a second spacer are formed to be closely connected to the first spacer and form the S/D region below the epitaxial silicon layer. A part of the epitaxial silicon layer is then transformed into a metal silicide layer, so as to complete the process of the field effect transistor.

Claims

1. A method of fabricating a field effect transistor, comprising steps of:

providing a substrate comprising a gate thereon, wherein the gate includes a dielectric layer on the substrate and an electrode on the dielectric layer;

forming a liner oxide layer adjacent to and covering a sidewall of the gate;

forming a first spacer adjacent to the liner oxide layer;

forming an epitaxial silicon layer aside of the first spacer on the substrate;

forming a shallow source/drain (S/D) extension junction in the substrate below the epitaxial silicon layer, wherein the epitaxial silicon layer is formed before the shallow S/D extension junction is formed;

forming a second spacer covering the first spacer;

forming a S/D region aside of the second spacer in the substrate below the epitaxial silicon layer; and

transforming a part of the epitaxial silicon layer into a metal silicide layer.

2. The fabricating method of claim 1, wherein the method of forming the epitaxial silicon layer includes chemical vapor deposition (CVD).

3. The fabricating method of claim 1, wherein the epitaxial silicon layer includes SiGe.

4. The fabricating method of claim 1, wherein the method of forming the shallow S/D extension junction includes implantation of ions whose conductivity is different from that of the substrate.

5. The fabricating method of claim 1, wherein the first spacer includes a nitride layer.

6. The fabricating method of claim 1, wherein the thickness of the liner oxide layer is about 50-200 Å

.

7. The fabricating method of claim 1, wherein the thickness of the first spacer is about 50-200 Å

.

8. The fabricating method of claim 1, wherein the method of forming the liner oxide layer and the first spacer includes anisotropic etching.

9. The fabricating method of claim 1, wherein the thickness of the oxide layer is about 50-300 Å

.

10. The fabricating method of claim 1, wherein the thickness of the second spacer is about 200-1500 Å

.

11. The fabricating method of claim 1, wherein the method of transforming the epitaxial silicon layer into the metal silicide layer includes:

forming a metal layer to cover the epitaxial silicon layer;

performing a high temperature thermal process to produce a nitridation reaction between the metal layer and the epitaxial silicon layer; and

removing the remaining metal layer.

12. A method of fabricating a metal silicide, comprising steps of:

providing a substrate;

forming an epitaxial silicon layer on the substrate;

forming a shallow source/drain (S/D) extension junction in the substrate below the epitaxial silicon layer, wherein the epitaxial silicon layer is formed before the shallow S/D extension junction is formed;

forming a S/D region in the substrate below the epitaxial silicon layer; and

transforming a part of the epitaxial silicon layer into a metal silicide layer.

13. The fabricating method of claim 12, wherein the method of forming the epitaxial silicon layer includes chemical vapor deposition (CVD).

14. The fabricating method of claim 12, wherein the method of forming the shallow S/D extension junction includes implantation of ions whose conductivity is different from that of the substrate.

15. The fabricating method of claim 12, wherein the method of transforming the epitaxial silicon layer into the metal silicide layer includes:

forming a metal layer to cover the epitaxial silicon layer;

performing a high temperature thermal process to produce a nitridation reaction between the metal layer and the epitaxial silicon layer; and

removing the remaining metal layer.

16. A method of fabricating a field effect transistor, comprising steps of:

providing a substrate comprising a gate thereon;

forming a liner oxide layer on a sidewall of the gate;

forming a first spacer on the liner oxide layer;

forming an epitaxial silicon layer on the substrate aside of the first spacer;

performing a first ion implantation on the substrate with the gate and the first spacer as a mask to form a shallow source/drain extension junction, wherein the epitaxial silicon layer is formed before the shallow source/drain extension junction is formed;

forming a second spacer covering the first spacer;

performing a second ion implantation on the substrate with the first spacer, the second spacer and the gate as a mask to form a source/drain region;

forming a metal layer over the substrate; and

transforming the metal layer and at least a part of the epitaxial silicon layer into a metal silicide layer.

17. The fabricating method of claim 16, wherein the first ion implantation step is performed with an ion concentration lighter than an ion concentration of the second ion implantation step.