Field effect transistor with non-floating body and method for forming same on a bulk silicon wafer

• US 6,229,187 B1
• Filed: 10/20/1999
• Issued: 05/08/2001
• Est. Priority Date: 10/20/1999
• Status: Expired due to Term

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Ju, Dong-Hyuk
• Primary Examiner(s): WOJCIECHOWICZ, EDWARD JOSEPH
• Application Number:
  US09/420,972
• Time in Patent Office: 566 Days
• Field of Search: 257/396, 257/397, 257/401, 257/513, 257/520, 257/901
• US Class Current: 257/396
• CPC Class Codes: H01L 21/26533 of electrically inactive species in silicon to make buried insulating layers
• CPC Class Codes: H01L 21/266 using masks H01L21/26586 takes precedence
• CPC Class Codes: H01L 21/76264 SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
• CPC Class Codes: H01L 21/823418 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/78609 for preventing leakage current H01L29/78618 takes precedence

Abstract

A silicon on insulator (SOI) wafer is formed with an unoxidized perforation in the insulating silicon dioxide buried oxide layer. A field effect transistor (FET) structure on the SOI wafer is located above the unoxidized perforation such that the unoxidized perforation provides for electrical coupling between the channel region of the FET with the bulk silicon substrate to eliminate the floating body effect caused by charge accumulation in the channel regions due to historical operation of the FET. The method of forming the FET includes masking a silicon wafer prior to an oxygen implantation process to form the unoxidized perforated buried oxide layer in the wafer.

Claims

1. A field effect transistor formed on a semiconductor substrate comprising:

a) an active region, including a central channel region and a source region and a drain region disposed on opposite sides of said central channel region;

b) an insulating buried oxide layer in said semiconductor substrate isolating at least a portion of the active region from the semiconductor substrate

c) a conductive perforation in the buried oxide layer electrically coupling the channel region to the semiconductor substrate; and

d) an insulating trench extending around the perimeter of the active region to isolate the active region from other structures formed on said semiconductor substrate;

wherein the conductive perforation is narrower than the central channel region in a direction from the source region to the drain region.

2. The field effect transistor of claim 1 wherein the central channel region, the conductive perforation, and the semiconductor substrate are all the same conductivity and the source region and drain region are of an opposite conductivity.

5. The transistor of claim 1, wherein the conductive perforation is narrower than the central channel region in any corresponding direction.

6. The transistor of claim 1, wherein the substrate, the active region, and the conductive perforation are all parts of a single piece of silicon.

7. The transistor of claim 1, wherein the insulating trench is an oxide-filled trench.

8. The transistor of claim 1, wherein the conductive perforation has a cross-sectional area less than a cross-sectional area of the channel region.

3. A semiconductor device including a plurality of field effect transistors formed on a semiconductor substrate, each transistor comprising:

a) an active region, including a central channel region and a source region and a drain region each on opposing sides of the central channel region;

b) a bridge region, with a cross section area smaller than a cross section of the central channel region, conductively coupling the central channel region with said semiconductor substrate; and

c) an insulator isolating said active body region and said bridge region from at least one other of said plurality of transistors.

4. The semiconductor device of claim 3 wherein the central channel region, the bridge region, and the semiconductor substrate are all the same conductivity and the source region and drain region are of an opposite conductivity.

9. The device of claim 3, wherein for each of the transistors the bridge region is narrower than the central channel region in a direction from the source region to the drain region.

10. The device of claim 9, wherein for each of the transistors the bridge region is narrower than the central channel region in any corresponding direction.

11. The device of claim 3, wherein the substrate, the active regions, and the bridge regions are all parts of a single piece of silicon.

12. The device of claim 3, further comprising a buried oxide layer perforated by the bridge regions.