Polarity shifting flash A/D converter and method

• US 6,232,907 B1
• Filed: 05/20/1999
• Issued: 05/15/2001
• Est. Priority Date: 05/29/1998
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Nagaraj, Krishnaswamy, Viswanathan, T. R.
• Primary Examiner(s): Tokar, Michael
• Assistant Examiner(s): Paik, Steven S.
• Application Number:
  US09/315,246
• Time in Patent Office: 726 Days
• Field of Search: 341/122, 341/127, 341/132, 341/155, 341/159
• US Class Current: 341/159
• CPC Class Codes: H03M 1/361 having a separate comparator and reference value for each quantisation level, i.e. full flash converter type

Abstract

An A/D converter which includes a sample-and-hold circuit having an input and an output, a zero-crossing detector having an input coupled to the output of the sample-and-hold circuit and having an output indicative of a change in polarity of an input signal thereto and a polarity reverser having an input coupled to the output of the sample-and-hold circuit, a control terminal coupled to and under control of the output of the zero-crossing detector and an output terminal. A bank of comparators, preferably in a first and second array, each have inputs respectively coupled to the output of the polarity reverser, each comparator having an output. An encoder preferably having first and second portions is coupled to the output of the comparator, the first array preferably coupled to the first encoder portion and the second array preferably coupled to the second encoder portion, the encoder having an output. A multiplexer is optionally coupled to the first and second encoder portions and responsive to a predetermined signal from the second encoder portion to select signals from the outputs of one of the first and second encoders. A pair of buffers are optionally provided, a first buffer coupled between the output of the sample-and-hold circuit and both the polarity reverser and the zero crossing detector and a second buffer coupled between the output of the sample-and-hold circuit and the second array of comparators. First and second switches are optionally provided, the first switches being operational only during a first repeating time window for coupling the first buffer to the zero crossing detector and the polarity reverser and coupling the second buffer to the second array of comparators and the second switches are operational only during a second repeating time window not overlapping the first time window for coupling said second buffer to said zero crossing detector and said polarity reverser.

Claims

1. An A/D converter, comprising:

a sample-and-hold circuit having an input and an output;

a zero-crossing detector having an input coupled to the output of the sample-and-hold circuit and having an output indicative of a change in polarity of an input signal thereto;

a polarity reverser having an input coupled to the output of the sample-and-hold circuit, a control terminal coupled to and under control of the output of the zero-crossing detector and an output terminal;

a bank of comparators, each comparator having inputs respectively coupled to the output of the polarity reverser and a reference voltage source, and each comparator having an output; and

an encoder having inputs respectively coupled to the outputs of the bank of comparators and an output.

2. The A/D converter of claim 1 wherein said bank of comparators comprises a first array of comparators coupled to said polarity reverser and a second array of comparators coupled to said sample-and-hold circuit and said encoder comprises a first encoder portion coupled to said first array of comparators and a second encoder portion coupled to said second array of comparators.

3. The A/D converter of claim 2 further including a multiplexer coupled to said first and second encoder portions and responsive to a predetermined signal from said second encoder portion to select signals from the outputs of one of said first and second encoders.

4. The A/D converter of claim 3 wherein said predetermined signal is indicative of an input amplitude below a predetermined value.

5. The A/D converter of claim 3 further including a first buffer coupled between the output of said sample-and-hold circuit and both said polarity reverser and said zero crossing detector and a second buffer coupled between the output of said sample-and-hold circuit and said second array of comparators.

6. The A/D converter of claim 4 further including a first buffer coupled between the output of said sample-and-hold circuit and both said polarity reverser and said zero crossing detector and a second buffer coupled between the output of said sample-and-hold circuit and said second array of comparators.

7. The A/D converter of claim 6 further including first switches operational only during a first repeating time window for coupling said first buffer to said zero crossing detector and said polarity reverser and coupling said second buffer to said second array of comparators and second switches operational only during a second repeating time window not overlapping said first time window for coupling said second buffer to said zero crossing detector and said polarity reverser.

8. An A/D converter, comprising:

a sample-and-hold circuit having an input and an output;

a zero-crossing detector having an input coupled to the output of the sample-and-hold circuit and having an output indicative of a change in polarity of an input signal thereto;

a reference voltage source;

a polarity reverser having an input coupled to the reference voltage source and said output terminal of said zero crossing detector to provide a reference voltage output of a polarity determined by said output of said zero crossing detector;

a bank of comparators comprising a first array of comparators and a second array of comparators, each comparator having inputs respectively coupled to the output of the polarity reverser and a reference voltage source, and each comparator having an output;

an encoder comprising a first encoder portion and a second encoder portion, said first encoder portion having inputs respectively coupled to the outputs of said first array of comparators and said second encoder portion having inputs respectively coupled to the outputs of said second encoder portion;

a first reference ladder coupled to the reference voltage output of said polarity reverser;

said output of said reference ladder and said output of said sample and hold circuit coupled to the input of said first array of comparators;

a second reference ladder coupled to said reference voltage source and having an output coupled to said second array of comparators along with said output of said sample and hold circuit.

9. The A/D converter of claim 8 further including a multiplexer coupled to said first and second encoder portions and responsive to a predetermined signal from said second encoder portion to select signals from the outputs of one of said first and second encoders.

10. The A/D converter of claim 9 wherein said predetermined signal is indicative of an input amplitude below a predetermined value.

11. The A/D converter of claim 8 further including a first buffer coupled between the output of said sample-and-hold circuit and both said polarity reverser and said zero crossing detector and a second buffer coupled between the output of said sample-and-hold circuit and said second array of comparators.

12. The A/D converter of claim 9 further including a first buffer coupled between the output of said sample-and-hold circuit and both said polarity reverser and said zero crossing detector and a second buffer coupled between the output of said sample-and-hold circuit and said second array of comparators.

13. The A/D converter of claim 10 further including a first buffer coupled between the output of said sample-and-hold circuit and both the input to said zero crossing detector and said first array of comparators and a second buffer coupled between the output of said sample-and-hold circuit and said second array of comparators.

14. The A/D converter of claim 11 further including a first buffer coupled between the output of said sample-and-hold circuit and both the input to said zero crossing detector and said first array of comparators and a second buffer coupled between the output of said sample-and-hold circuit and said second array of comparators.

15. The A/D converter of claim 12 further including a first buffer coupled between the output of said sample-and-hold circuit and both the input to said zero crossing detector and said first array of comparators and a second buffer coupled between the output of said sample-and-hold circuit and said second array of comparators.