Apparatus and method of PCI routing in a bridge configuration

• US 6,233,641 B1
• Filed: 06/08/1998
• Issued: 05/15/2001
• Est. Priority Date: 06/08/1998
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Moertl, Daniel Frank, Graham, Charles Scott, Movall, Paul Edward, Lambeth, Shawn Michael
• Primary Examiner(s): Beausoleil, Robert
• Assistant Examiner(s): PHAN, RAYMOND NGAN
• Application Number:
  US09/093,441
• Time in Patent Office: 1,072 Days
• Field of Search: 710/128-132, 710/31, 710/37, 710/38, 710/42, 710/20, 710/22, 710/126, 710/127, 710/107, 710/110, 710/36, 710/27
• US Class Current: 710/316
• CPC Class Codes: G06F 13/4022 using switching circuits, e.g. switching matrix, connection or expansion network G06F13/4009 takes precedence
• CPC Class Codes: G06F 13/4045 where the bus bridge performs an extender function

Abstract

A primary PCI bus and multiple secondary PCI busses of a PCI expansion card interface, are interconnected by a routing circuit. The routing circuit functions as a switched bridge between the primary PCI bus and each of the secondary PCI busses, respectively, by associating each secondary PCI bus with an address range, and forwarding a command received from the primary PCI bus to a secondary PCI bus mapped to an address range including the address of the command. Furthermore, the routing circuit forwards commands intended for the primary PCI bus from the secondary PCI busses. In addition, the routing circuit directly routes commands between the secondary PCI busses, when commands received from one secondary PCI bus are intended for another PCI bus, without use of the primary bus. As a result, traffic and latency on the primary PCI bus is reduced and efficiency is increased.

Claims

1. A routing circuit for interconnecting a primary computer expansion bus and first and second secondary computer expansion busses for forwarding commands between the primary and secondary computer expansion busses, each command having an address, comprising

a multi-way switch interconnecting the primary bus and first and second secondary busses,

a memory storing entries mapping each bus to at least one address range, and

a control circuit, the control circuit controlling the multi-way switch to forward commands between the primary and secondary busses in response to the address of the command and entries stored in the memory, the control circuit:

controlling the multi-way switch to forward a command received from the primary bus having an address within an address range mapped to a secondary bus, to that secondary bus,

controlling the multi-way switch to forward a command received from a secondary bus having an address within an address range mapped to the primary bus, to the primary bus, and

controlling the multi-way switch to forward a command received from the first secondary bus having an address within an address range mapped to the second secondary bus, to the second secondary bus, without use of the primary bus;

whereby traffic and latency on the primary bus due to commands sent from one secondary bus to another, is reduced.

2. The routing circuit of claim 1 wherein the memory comprises

control registers specifying address ranges for commands received on the primary bus which map to the first and second secondary busses, the control circuit forwarding a command received from the primary bus having an address within an address range mapped by a control register to a secondary bus, to that secondary bus, and

a routing table of entries, each entry specifying an address range for commands received on a secondary bus which map to another bus, the control circuit forwarding a command received from a secondary bus having an address within an address range mapped by a routing table entry to another bus, to that other bus.

3. The routing circuit of claim 2 further comprising additional secondary busses, each connected to the multi-way switch in the routing circuit.

4. The routing circuit of claim 2 wherein in the routing table includes a plurality of entries for a secondary bus, each entry specifying an address range and mapping to a bus to which commands with addresses in the range should be forwarded.

5. The routing circuit of claim 4 wherein the memory further comprises enable registers, the enable registers identifying which of the routing table entries are enabled, and

the control circuit responds to a command received from a secondary bus by comparing an address of the command to any enabled entries for the secondary bus, and when the address of the command is determined to be within an address range of a matching entry, the command is forwarded to the bus mapped by the address range of the matching entry.

6. The routing circuit of claim 5 wherein, if there are no enabled routing table entries for a secondary bus, the control circuit routes commands from the secondary bus to the primary bus only if the address of the command is not in the range mapped by a control register to the secondary bus.

7. The routing circuit of claim 4 wherein the routing table includes at least two entries for a secondary bus, each entry mapping an address range to an other bus, and

the control circuit responds to a command received from a secondary bus by comparing an address of the command to each of the entries for the secondary bus, and when the address of the command is determined to be within an address range of a matching entry, the command is forwarded to the bus mapped by the address range of the matching entry.

8. The routing circuit of claim 4 wherein commands received from the primary or secondary bus include input/output commands and memory access commands, and the routing table includes at least two entries for input/output commands for a secondary bus, and at least two entries for memory access commands for a secondary bus, each entry mapping an address range to an other bus, and

the control circuit responds to an input/output command received from the secondary bus by comparing an address of the command to each of the entries for input/output commands for the secondary bus, and when the address of the command is determined to be within an address range of a matching entry, the command is forwarded to the bus mapped by the address range of the matching entry, and

the control circuit responds to a memory access command received from the secondary bus by comparing an address of the command to each of the entries for memory access commands for the secondary bus, and when the address of the command is determined to be within an address range of a matching entry, the command is forwarded to the bus mapped by the address range of the matching entry.

9. The routing circuit of claim 2 wherein the routing table entries further specify an address offset to be applied to forwarded commands, and

the control circuit, upon matching a command from a secondary bus having an address within an address range mapped in a routing table entry to another bus, modifies the address of the command in accordance with the address offset in the routing table entry, and then forwards the modified command to that other bus.

10. The routing circuit of claim 2 wherein the routing table entries further specify pre-fetching activities to be performed when forwarding read commands which read memory locations, and

the control circuit, upon matching a read command from a secondary bus to an address range mapped in a matching routing table entry to an other bus, generates commands to that other bus which read additional memory locations not initially requested by the read command, based upon pre-fetching activities specified in the matching routing table entry.

11. The routing circuit of claim 10 wherein the multi-way switch further comprises a data buffer for buffering the contents of additional memory locations read as part of pre-fetching activities specified in a routing table entry.

12. The routing circuit of claim 2 wherein the routing table entries further specify write block sizes to be used when forwarding write commands which write data into addressed memory locations, and

the control circuit, upon matching a write command from a secondary bus to an address range mapped in a routing table entry to an other bus, combines the data for the write command with data obtained from other write commands, and writes the combined data over the other bus.

13. The routing circuit of claim 12 wherein the multi-way switch further comprises a data buffer for buffering data for multiple write commands being combined.

14. A method for forwarding commands between a primary computer expansion bus and first and second secondary computer expansion busses, each command having an address, comprising

mapping each bus to at least one address range, and

forwarding a command received from the primary bus having an address within an address range mapped to a secondary bus, to that secondary bus,

forwarding a command received from a secondary bus having an address within an address range mapped to the primary bus, to the primary bus, and

forwarding a command received from the first secondary bus having an address within an address range mapped to the second secondary bus, to the second secondary bus, without use of the primary bus;

whereby traffic and latency on the primary bus due to commands sent from one secondary bus to another, is reduced.

15. The method of claim 14 further comprising

mapping address ranges for commands received on the primary bus to the first and second secondary busses, and forwarding a command received from the primary bus having an address within an address range mapped to a secondary bus, to that secondary bus, and

mapping, for a secondary bus, an address range for commands received on the secondary bus to an other bus, and forwarding a command received from a secondary bus having an address within an address range mapped to an other bus, to that other bus.

16. The method of claim 15 further comprising mapping a plurality of address ranges for a secondary bus, each address range being mapped to an other bus, commands from the secondary bus with addresses in a range, being forwarded to an other bus mapped by the range.

17. The method of claim 16 further comprising responding to a command received from a secondary bus by comparing an address of the command to each of the address ranges for the secondary bus, and when the address of the command is determined to be within a matching address range, forwarding the command to an other bus mapped by the matching range.

18. The method of claim 17 further comprising, if there are no address ranges for a secondary bus, routing commands from the secondary bus to the primary bus only if the address of the command is not in the range mapped to the secondary bus for commands received from the primary bus.

19. The method of claim 16 wherein at least two address ranges for a secondary bus are mapped to other busses, further comprising comparing an address of a command from the secondary bus to each of the address ranges for the secondary bus, and when the address of the command is determined to be within an address range mapped to an other bus, forwarding the command to the bus mapped by the address range.

20. The method of claim 16 wherein commands received from the primary or secondary bus include input/output commands and memory access commands, and wherein at least two address ranges for input/output commands received from a secondary bus, are mapped to other busses, and at least two address ranges for memory access commands from the secondary bus, are mapped to other busses, further comprising

responding to an input/output command received from the secondary bus by comparing an address of the command to each of the address ranges for input/output commands for the secondary bus, and when the address of the command is determined to be within an address range of a matching entry, forwarding the command to the bus mapped by the address range of the matching entry, and

responding to a memory access command received from the secondary bus by comparing an address of the command to each of the address ranges for memory access commands for the secondary bus, and when the address of the command is determined to be within an address range of a matching entry, forwarding the command to the bus mapped by the address range of the matching entry.

21. The method of claim 14 wherein an address offset is applied to at least some commands which are forwarded.

22. The method of claim 14 wherein as part of forwarding a read command which reads memory locations, commands are generated to pre-fetch additional memory locations not initially requested by the read command.

23. The method of claim 22 further comprising buffering the contents of additional memory locations that are pre-fetched.

24. The method of claim 14 wherein as part of forwarding a write command which writes data into addressed memory locations, the data is combined with data for contiguous memory locations obtained from other write commands, and then the combined data is written contiguously.

25. The method of claim 24 further comprising buffering data for multiple write commands being combined.