Circuit synthesis time budgeting based upon wireload information

• US 6,233,724 B1
• Filed: 10/30/1998
• Issued: 05/15/2001
• Est. Priority Date: 10/30/1998
• Status: Expired due to Term

• Current Assignee: Ovonyx Memory Technology, LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: LaBerge, Paul A.
• Primary Examiner(s): Smith, Matthew
• Assistant Examiner(s): Kik, Phallaka
• Application Number:
  US09/183,782
• Time in Patent Office: 928 Days
• Field of Search: 716/1-21
• US Class Current: 716/104
• CPC Class Codes: G06F 30/327 Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist

Abstract

One embodiment of the present invention provides a system for synthesizing a circuit that allocates propagation delay between modules in the circuit based upon wireload information. The system receives a circuit divided into modules coupled together by a number of signal lines. The system defines a first set of timing constraints, and uses the first set of timing constraints to compile the circuit from a hardware description language specification into a first gate-level implementation. Next, the system performs a timing analysis on the first gate-level implementation to determine positive or negative slack values for the signal lines. These slack values specify amounts of extra propagation delay available on the signal lines. Next, the slack values are used to define a second set of timing constraints by allocating the slack values between the modules based upon wireload information. This wireload information may include such parameters as gate delays and drive strengths for gates coupled to the signal lines. The second set of timing constraints is used to compile the circuit into a second gate-level implementation. If necessary, the process of compilation, timing analysis and allocation of slack values may be repeated until the circuit meets all timing constraints.

Claims

1. A method for synthesizing a circuit that allocates propagation delay between modules in the circuit based upon wireload information, comprising:

receiving the circuit, the circuit being divided into a plurality of modules coupled together by a plurality of signal lines;

defining a first set of timing constraints for the plurality of signal lines;

compiling the circuit from a hardware description language specification into a first gate-level implementation using the first set of timing constraints;

performing a timing analysis on the first gate-level implementation to determine a first set of slack values for the plurality of signal lines, wherein the first set of slack values specify amounts of extra propagation delay that are available on the plurality of signal lines;

defining a second set of timing constraints based upon wireload information, wherein defining the second set of timing constraints includes for a given signal line that couples together a first module and a second module,

examining gates on a signal path that passes through the given signal line,

calculating for each gate on the signal path a weight, which is a function of gate delay and gate drive strength,

calculating a first sum of weights for gates on the signal path within the first module,

calculating a second sum of weights for gates on the signal path within the second module, and

allocating a slack value associated with the given signal line between the first module and the second module in proportion to relative values of the first sum and the second sum;

wherein the wireload information includes gate delays and drive strengths for gates coupled to the plurality of signal lines; and

compiling the circuit from the hardware description language specification into a second gate-level implementation using the second set of timing constraints.

2. The method of claim 1, wherein the act of determining the first set of slack values includes determining slack values that can be positive or negative, a positive slack value indicating that extra propagation delay is available on a corresponding signal line, and a negative slack value indicating that a propagation delay on the corresponding signal line violates a timing constraint.

3. The method of claim 1, wherein the wireload information includes a number of loads on the given signal line.

4. The method of claim 1, wherein the wireload information includes capacitive loading information for signal lines.

5. The method of claim 1, wherein the wireload information includes resistive loading information for signal lines.

6. The method of claim 1, wherein at least part of the wireload information is retrieved from a table that is indexed by gate-level drive strength and propagation delay.

7. The method of claim 1, wherein the act of defining the first set of timing constraints includes defining default values for the first set of timing constraints.

8. The method of claim 1, wherein the act of defining the first set of timing constraints includes estimating the first set of timing constraints by examining logic equations for the circuit.

9. The method of claim 1, further comprising:

performing a timing analysis on the second gate-level implementation to determine a second set of slack values for the plurality of signal lines;

defining a third set of timing constraints by allocating the second set of slack values between the plurality of modules based upon wireload information; and

compiling the circuit from the hardware description language specification into a third gate-level implementation using the third set of timing constraints.

10. The method of claim 9, further comprising iteratively repeating the acts of performing the timing analysis on the second gate level implementation, defining the third set of timing constraints and compiling the circuit into the third gate-level implementation until the circuit satisfies the third set of timing constraints.

11. The method of claim 1, wherein compiling the circuit from the hardware description language specification, includes compiling the circuit from a VHDL specification.

12. The method of claim 1, wherein compiling the circuit from the hardware description language specification, includes compiling the circuit from a VERILOG specification.

13. A method for synthesizing a circuit that allocates propagation delay between modules in the circuit based upon wireload information, comprising:

receiving the circuit, the circuit being divided into a plurality of modules coupled together by a plurality of signal lines;

estimating a first set of timing constraints by examining logic equations for the circuit;

compiling the circuit from a hardware description language specification into a first gate-level implementation using the first set of timing constraints;

performing a timing analysis on the first gate-level implementation to determine a first set of slack values for the plurality of signal lines, wherein the first set of slack values specify amounts of extra propagation delay that are available on the plurality of signal lines;

defining a second set of timing constraints based upon wireload information, wherein defining the second set of timing constraints includes for a given signal line that couples together a first module and a second module,

examining gates on a signal path that passes through the given signal line,

calculating for each gate on the signal path a weight, which is a function of gate delay and gate drive strength,

calculating a first sum of weights for gates on the signal path within the first module,

calculating a second sum of weights for gates on the signal path within the second module, and

allocating a slack value associated with the given signal line between the first module and the second module in proportion to relative values of the first sum and the second sum;

wherein the wireload information includes gate delays and drive strengths for gates coupled to the plurality of signal lines, and at least part of the wireload information is retrieved from a table that is indexed by gate-level drive strength and propagation delay;

compiling the circuit from the hardware description language specification into a second gate-level implementation using the second set of timing constraints; and

iteratively repeating the acts of performing the timing analysis, defining timing constraints and compiling the circuit until the circuit satisfies a set of timing constraints.

14. A computer readable storage medium storing instructions that when executed by a computer cause the computer to perform a method for synthesizing a circuit that allocates propagation delay between modules in the circuit based upon wireload information, comprising:

receiving the circuit, the circuit being divided into a plurality of modules coupled together by a plurality of signal lines;

defining a first set of timing constraints for the plurality of signal lines;

compiling the circuit from a hardware description language specification into a first gate-level implementation using the first set of timing constraints;

performing a timing analysis on the first gate-level implementation to determine a first set of slack values for the plurality of signal lines, wherein the first set of slack values specify amounts of extra propagation delay that are available on the plurality of signal lines;

defining a second set of timing constraints based upon wireload information, wherein defining the second set of timing constraints includes for a given signal line that couples together a first module and a second module,

examining gates on a signal path that passes through the given signal line,

calculating for each gate on the signal path a weight, which is a function of gate delay and gate drive strength,

calculating a first sum of weights for gates on the signal path within the first module,

calculating a second sum of weights for gates on the signal path within the second module, and

allocating a slack value associated with the given signal line between the first module and the second module in proportion to relative values of the first sum and the second sum;

wherein the wireload information includes gate delays and drive strengths for gates coupled to the plurality of signal lines; and

compiling the circuit from the hardware description language specification into a second gate-level implementation using the second set of timing constraints.

15. An apparatus for synthesizing a circuit that allocates propagation delay between modules in the circuit based upon wireload information, comprising:

a receiving mechanism, that receives the circuit, the circuit being divided into a plurality of modules coupled together by a plurality of signal lines;

an initial constraint generator that defines a first set of timing constraints for the plurality of signal lines;

a compiler that compiles the circuit from a hardware description language specification into a first gate-level implementation using the first set of timing constraints;

a timing analyzer that performs a timing analysis on the first gate-level implementation to determine a first set of slack values for the plurality of signal lines, wherein the first set of slack values specify amounts of extra propagation delay that are available on the plurality of signal lines;

a time budgeting mechanism that defines a second set of timing constraints based upon wireload information, such that a given slack value associated with a given signal line is allocated between modules coupled to the given signal line, wherein the time budgeting mechanism is configured to,

examine gates in a signal path that passes through a given signal line that couples together a first module and a second module,

calculate for each gate on the signal path a weight, which is a function of gate delay and drive strength,

calculate a first sum of weights for gates on the signal path within the first module,

calculate a second sum of weights for gates on the signal path within the second module, and

allocate a slack value associated with the signal line between the first module in proportion to relative values of the first sum and the second sum;

wherein the wireload information includes gate delays and drive strengths for gates coupled to the plurality of signal lines; and

wherein the compiler compiles the circuit from the hardware description language specification into a second gate-level implementation using the second set of timing constraints.

16. The apparatus of claim 15, wherein slack values can be positive or negative, a positive slack value indicating that extra propagation delay is available on a corresponding signal line, and a negative slack value indicating that a propagation delay on the corresponding signal line violates a timing constraint.

17. The apparatus of claim 15, wherein the wireload information includes a number of loads on a given signal line.

18. The apparatus of claim 15, wherein the wireload information includes capacitive loading information for signal lines.

19. The apparatus of claim 15, wherein the wireload information includes resistive loading information for signal lines.

20. The apparatus of claim 15, wherein at least part of the wireload information is retrieved from a table that is indexed by gate-level drive strength and propagation delay.

21. The apparatus of claim 15, wherein the initial constraint generator is configured to define the first set of timing constraints using default values.

22. The apparatus of claim 15, wherein the initial constraint generator is configured to estimate the first set of timing constraints by examining logic equations for the circuit.

23. The apparatus of claim 15, further comprising a control mechanism that is configured to repeat the acts of performing the timing analysis, defining the second set of timing constraints and compiling the circuit until the circuit satisfies the second set of timing constraints.

24. The apparatus of claim 15, wherein the hardware description language specification includes a VHDL specification.

25. The apparatus of claim 15, wherein the hardware description language specification includes a VERILOG specification.