Line receiver circuit with large common mode range for differential input signals

• US 6,236,242 B1
• Filed: 02/24/2000
• Issued: 05/22/2001
• Est. Priority Date: 08/25/1997
• Status: Expired due to Term

• Current Assignee: Telefonaktiebolaget LM Ericsson
• Original Assignee: Telefonaktiebolaget LM Ericsson
• Inventors: Hedberg, Mats
• Primary Examiner(s): Cunningham, Terry D.
• Assistant Examiner(s): NGUYEN, LONG T
• Application Number:
  US09/512,330
• Time in Patent Office: 453 Days
• Field of Search: 327/52-53, 327/65, 327/66, 327/359, 327/50, 327/63, 327/355, 327/563, 327/108-112
• US Class Current: 327/65
• CPC Class Codes: H03F 3/45479 characterised by the way of common mode signal rejection
• CPC Class Codes: H03F 3/45708 Controlling the common source circuit of the differential amplifier
• CPC Class Codes: H03F 3/45717 Controlling the loading circuit of the differential amplifier
• CPC Class Codes: H04L 25/0276 Arrangements for coupling common mode signals
• CPC Class Codes: H04L 25/0292 Arrangements specific to the receiver end

Abstract

A line receiver circuit for receiving differential digital signals from a symmetrical transmission line comprises a first differential input stage (1) adapted to receive and process differential signals having a common mode voltage within a first common mode voltage range, and a second differential input stage (2) adapted to receive and process differential signals having a common mode voltage within a second common mode voltage range. Means (N5, N6) detect an operating condition of said first input stage (1) which operating condition depends on a common mode input voltage at said inputs of said first input stage. Means (P1, N7, N8) are provided for enabling said second input stage depending on said detected operating condition of said first input stage.

Claims

1. A line receiver circuit for receiving differential digital signals from a symmetrical transmission line, having a pair of differential input terminals for connection with said transmission line and having an output for outputting data signals corresponding to signals received via said transmission line, said line receiver circuit comprising:

a first differential input stage having a first pair of differential inputs connected to receive input signals from said pair of differential input terminals;

said first input stage being adapted to receive and process differential signals having a common mode voltage within a first lower common mode voltage range;

a second differential input stage having a second pair of differential inputs connected to receive input signals from said pair of differential input terminals;

said second input stage being adapted to receive and process differential signals having a common mode voltage within a second higher common mode voltage range wherein the second higher common mode voltage range is at least partially greater or higher than the first lower common mode voltage range of the first input stage;

means for combining output signals provided by said first differential input stage and output signals provided by said second differential input stage;

means for detecting an operating condition of said first input stage which operating condition depends on a common mode input voltage at said inputs of said first input stage, wherein the detected operating condition indicates when the first input stage reaches an upper limit of the first lower common mode voltage range; and

means for enabling said second input stage depending on said detected operating condition of said first input stage so that the second input stage is enabled when said means for detecting detects that the common mode input voltage reaches the upper limit of the first lower common mode voltage range of the first input stage, so that operation of the second input stage for the second higher common mode voltage is inhibited until the upper limit of the first input stage for the lower common mode voltage range has been reached.

2. A line receiver circuit according to claim 1, further comprising:

a first current source circuit;

said detected operating condition being the amount of an operating current supplied by said first current source circuit into said first input stage.

3. A line receiver circuit according to claim 2, wherein said means for detecting said operating condition of said first input stage comprises a current mirror circuit for providing a mirror current of the current actually supplied by said first current source circuit into said first input stage.

4. A line receiver circuit according to claim 3, wherein said current mirror circuit comprises

a first current mirror circuit associated with a first one of said input terminals of said line receiver circuit and having a control current input and a mirror current input;

a second current mirror circuit associated with the other one of said input terminals (A, B) of said line receiver circuit and having a control current input and a mirror current input;

said control current input of said first current mirror circuit and said control current input of said second current mirror circuit being connected to divide a current supplied by said first current source circuit; and

said first and said second current mirror circuits being connected with the input terminals such that a ratio between said control current flowing into said first current mirror circuit and said control current flowing into said second current mirror circuit depends on a potential difference across said input terminals.

5. A line receiver circuit according to claim 4, wherein

said mirror current inputs of said first and second current mirror circuits (N1, N5;

N2, N6) are connected together to provide a first mirror current (I4); and

means (CI2, N7, N8, P1) for enabling or disabling the second differential input stage (N9, N10) adapted to enable said second input stage depending on said first mirror current (I4).

6. A line receiver circuit according to claim 4 further comprising

a second current source circuit (CI2) for providing a second current (I5);

said second current source circuit (CI2) being connected to feed said mirror current inputs of said first and second current mirror circuits (N1, N5;

N2, N6);

a shunt circuit (P1, N7) for taking a shunt current (I5-I4) supplied by said second current source circuit (CI2) and not taken by said mirror current inputs;

means (CI2, N7, N8, P1) for enabling or disabling the second differential input stage (N9, N10) being adapted to enable said second input stage depending on said shunt current (I5-I4).

7. A line receiver circuit according to claim 1 wherein the second input stage comprises

a difference amplifier comprising a first transistor (N9) connected to receive at its gate a signal from said first input terminal (A), and a second transistor (N10) connected to receive at its gate a signal from said second input terminal (B).

8. A line receiver circuit according to claim 7, wherein said means for enabling said second input stage comprises

a third current mirror circuit (N7, N8) connected to receive at its control current input said shunt current (I5-I4);

said first and second transistors (N9, N10) of said difference amplifier circuit being connected to the mirror current input of said third current mirror.

9. A line receiver circuit according to claim 8, comprising means (P1) for keeping a voltage at the output of said second current source at a predetermined potential.

10. The line receiver circuit according to claim 1, wherein said current mirror circuits are of a cascode type.

11. A line receiver circuit for receiving differential digital signals from a symmetrical transmission line, having a pair of differential input terminals for connection with said transmission line and having an output for outputting data signals corresponding to signals received via said transmission line, said line receiver circuit comprising:

a first differential input stage having a first pair of differential inputs connected to receive input signals from said pair of differential input terminals;

said first input stage being adapted to receive and process differential signals having a common mode voltage within a first lower common mode voltage range;

a second differential input stage having a second pair of differential inputs connected to receive input signals from said pair of differential input terminals;

said second input stage being adapted to receive and process differential signals having a common mode voltage within a second higher common mode voltage range, wherein the second higher common mode voltage range is at least partially greater or higher than the first lower common mode voltage range of the first input stage;

a circuit for combining output signals provided by said first differential input stage and output signals provided by said second differential input stage;

a circuit for detecting an operating condition of said first input stage which operating condition depends on a common mode input voltage at said inputs of said first input stage, wherein the detected operating condition indicates when the first input stage reaches an upper limit of the first lower common mode voltage range; and

a circuit for selectively activating said second input stage depending on said detected operating condition of said first input stage so that the second input stage is active when said circuit for detecting detects that the common mode input voltage reaches the upper limit of the first lower common mode voltage range of the first input stage, so that operation of the second input stage for the second higher common mode voltage is inhibited until the upper limit of the first input stage for the lower common mode voltage range has been reached.

12. A method of operating a line receiver circuit for receiving differential digital signals from a symmetrical transmission line, the line receiver circuit having a pair of differential input terminals for connection with said transmission line and having an output for outputting data signals corresponding to signals received via said transmission line, said method comprising:

providing the line receiver circuit with a first differential input stage having a first pair of differential inputs connected to receive input signals from said pair of differential input terminals, and a second differential input stage having a second pair of differential inputs connected to receive input signals from said pair of differential input terminals;

the first input stage receiving and processing differential signals having a common mode voltage within a first lower common mode voltage range;

the second input stage receiving and processing differential signals having a common mode voltage within a second higher common mode voltage range, wherein the second higher common mode voltage range is at least partially greater or higher than the first lower common mode voltage range;

combining output signals provided by said first differential input stage and output signals provided by said second differential input stage;

detecting an operating condition of said first input stage which operating condition depends on a common mode input voltage at said inputs of said first input stage, wherein the detected operating condition indicates when the first input stage reaches an upper limit of the first lower common mode voltage range; and

selectively activating the second input stage depending on said detected operating condition of said first input stage so that the second input stage is active when it is detected that the common mode input voltage reaches the upper limit of the first lower common mode voltage range of the first input stage, so that operation of the second input stage for the second higher common mode voltage is inhibited until the upper limit of the first input stage for the lower common mode voltage range has been reached.