Switched body SOI (silicon on insulator) circuits and fabrication method therefor

• US 6,239,649 B1
• Filed: 04/20/1999
• Issued: 05/29/2001
• Est. Priority Date: 04/20/1999
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Mandelman, Jack Allan, Nowak, Edward Joseph, Tonti, William Robert, Ellis-Monaghan, John Joseph, Hook, Terence Blackwell, Pricer, Wilbur David, Bertin, Claude Louis, Tong, Minh Ho, Hedberg, Erik Leigh
• Primary Examiner(s): Callahan, Timothy P.
• Assistant Examiner(s): Luu, An T.
• Application Number:
  US09/295,124
• Time in Patent Office: 770 Days
• Field of Search: 327/534, 327/535, 327/536, 327/537, 326/112, 326/119, 326/31, 326/33, 326/34
• US Class Current: 327/534
• CPC Class Codes: H01L 29/78606 with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device H01L29/78642, H01L29/78645 take precedence
• CPC Class Codes: H03K 19/0027 in field effect transistor circuits
• CPC Class Codes: H03K 2217/0018 Special modifications or use of the back gate voltage of a FET

Abstract

Circuits with SOI devices are coupled to a body bias voltage via a switch for selectively connecting the body bias voltage signals to the SOI device body. NMOS or PMOS SOI devices are used for the switched body SOI device and a FET is used for the switch and the gate terminal of the SOI device is connected to the FET device. The gate of the SOI device controls the FET switch connection of the body bias voltage signals to the SOI device to adjust the threshold value of the SOI device. Logic circuits incorporating the SOI devices are also disclosed, and the fabrication process for the SOI devices as well.

Claims

1. A complementary pass gate logic circuit including a plurality of switched body SOI unit cells comprising:

at least four switched body SOI unit cells each including at least two FET devices with the gate of one FET device connected to the gate of a second FET device;

a first logic signal A input means connected to a first one of said switched body SOI unit cells;

a second logic signal B input means connected to said first one and to second and a third ones of said switched body SOI unit cells;

a third logic signal NOT A input signal means connected to said third switched body SOI unit cell;

a fourth logic signal NOT B input means connected to said second and to a fourth one of said switched body SOI unit cells;

a first inverter buffer circuit connected to the output of said first and second switched body SOI unit cells to provide a NOT Q=(NOT A)×

(NOT B) output logic signal; and

a second inverter buffer circuit connected to the output of said third and fourth switched body SOI unit cells to provide a Q=(A)×

(B) output logic signal.

2. A circuit according to claim 1 wherein said switched body SOI unit cells include a first SOI FET having a gate connected to an input for receiving an input signal and for turning on and off in response thereto;

a second FET having a gate and diffusion regions, the gate of the second FET being connected to the input for receiving the input signal, one of the diffusion regions of the second FET being connected to a body of the first FET;

a voltage terminal having a voltage level, another of the diffusion regions of the second FET being connected to the voltage terminal for connecting the voltage level to the body of the first FET for adjusting a voltage threshold of the first FET in response to the input signal simultaneously with said turning on and off.

3. The circuit of claim 1 wherein said first and second FETs are enhancement mode FETs.

4. A circuit according to claim 1 wherein said four switched body SOI unit cells include a first SOI FET device having a body, and gate, source and drain electrodes connected to said body;

at least one source of body bias voltage;

at least one switching means connected between said body of said FET device and said at least one source of body bias voltage for selectively connecting said body bias voltage to said FET device for adjusting a threshold voltage level of said FET device;

and means for connecting said at least one switching means to said gate electrode of said FET device for controlling the at least one switching means for connecting said body bias voltage to said FET body.

5. The circuit of claim 4 wherein said at least one switching means is an FET switch having source, drain and gate electrodes wherein said connecting means connects said gate electrode of said FET switch to said gate electrode of said SOI FET device for turning said FET switch on and off.

6. The circuit of claim 5 wherein said SOI FET device is a NFET.

7. The circuit of claim 5 wherein said SOI FET device is a PFET.

8. The circuit of claim 5 wherein said FET switch connects said body bias voltage to said SOI FET device to lower the threshold voltage of said SOI FET device.

9. The circuit of claim 5 wherein said FET switch connects said body bias voltage to said SOI FET device to raise the threshold voltage of said SOI FET device.

10. A circuit according to claim 1 wherein said switched body SOI unit cells include a first-type FET device having a gate coupled to an input for receiving an input signal;

a second-type FET device having a gate coupled to said input for receiving said input signal, and coupled to the body of said first-type FET device for adjusting in a first direction a voltage threshold of said first-type FET device in response to said input signal; and

a second, first-type FET device having a gate coupled to said input for receiving said input signal and coupled to said body of said first, first-type FET device for adjusting in a second direction said voltage threshold of said first, first-type FET device in response to said input signal.