Method and apparatus for gate-level simulation of synthesized register transfer level designs with source-level debugging

CAFC
  • US 6,240,376 B1
  • Filed: 07/31/1998
  • Issued: 05/29/2001
  • Est. Priority Date: 07/24/1998
  • Status: Expired due to Term
First Claim
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1. A method comprising the steps of:

  • a) identifying at least one statement within a register transfer level (RTL) synthesizable source code; and

    b) synthesizing the source code into a gate-level netlist including at least one instrumentation signal, wherein the instrumentation signal is indicative of an execution status of the at least one statement.

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