Methods and circuits for restoration of a drooped DC signal

• US 6,242,961 B1
• Filed: 10/08/1999
• Issued: 06/05/2001
• Est. Priority Date: 10/08/1998
• Status: Expired due to Term

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Altima Communications, Inc. (Broadcom, Inc.)
• Inventors: Liu, James, Fang, Wen, Wu, Wen-Chung
• Primary Examiner(s): LE, DINH THANH
• Application Number:
  US09/415,680
• Time in Patent Office: 606 Days
• Field of Search: 327/99, 327/307, 327/165, 327/141, 327/306, 327/168
• US Class Current: 327/307
• CPC Class Codes: H03K 5/007 Base line stabilisation thresholding H03K5/08
• CPC Class Codes: H04L 25/063 Setting decision thresholds using feedback techniques only

Abstract

Circuits for the restoration of a drooped signal are disclosed. In the asynchronous mode circuit, the drooped signal can be restored by detecting the peak of the positive amplitude and the peak of the negative amplitude and take the difference between the two peaks. This difference signal is fed back the equalizer. In the synchronous mode circuit, the drooped signal is sliced and passed to a regeneration circuit. The regeneration circuit uses reference voltage signals and phase information from the slicer to generate a regenerated signal. The regenerated signal is compared with the equalized signal to generate a difference signal, again fed back to the equalizer. The sliced signal is also fed to a clock recovery circuit which recovers the clock signal embedded in the received signal. The two circuits can be combined to provide an optimal circuit for the restoration of a drooped signal.

Claims

1. A circuit for correcting a drooped DC signal, said circuit comprising:

an asynchronous drooping correcting subcircuit, receiving said drooped DC signal and outputting a first corrected signal;

a synchronous drooping correcting subcircuit, receiving said drooped DC signal and outputting a second corrected signal;

a multiplexer, receiving said first corrected signal and said second corrected signal;

data lock signal generating means generating a data lock signal, supplied to the multiplexer, wherein said multiplexer selects said first corrected signal or said second corrected signal based on the data lock signal; and

an equalizer, receiving said drooped DC signal and a signal selected by said multiplexer and outputting an output corrected signal which is a sum of the received signals.

2. A circuit for correcting a drooped DC signal according to claim 1, wherein said asynchronous drooping correcting subcircuit determines a difference between a peak positive amplitude of said drooped DC signal and a peak negative amplitude of said drooped DC signal and said first corrected signal is proportional to said difference.

3. A circuit for correcting a drooped DC signal according to claim 1, wherein said synchronous drooping correcting subcircuit comprises:

a slicer, which receives said drooped DC signal, separates negative and positive equalized portions of said drooped DC signal, generates a NRZI signal based on a sum of said negative and positive equalized portions, outputs said NRZI signal to said data lock signal generating means, and outputs said negative and positive equalized portions;

a regeneration circuit, which receives said negative and positive equalized portions and generates a regenerated signal based on predetermined signals supplied by a band gap reference circuit; and

a substractor, receiving said regenerated signal and said drooped DC signal and producing a difference signal proportional to the difference between said regenerated signal and said drooped DC signal;

wherein said second corrected signal is said difference signal.