Method to reduce reset noise in photodiode based CMOS image sensors

• US 6,243,134 B1
• Filed: 02/27/1998
• Issued: 06/05/2001
• Est. Priority Date: 02/27/1998
• Status: Expired due to Term

• Current Assignee: Intel Corporation, Oracle Corporation
• Original Assignee: Intel Corporation
• Inventors: Beiley, Mark A.
• Primary Examiner(s): Garber, Wendy R.
• Assistant Examiner(s): MOE, AUNG SOE
• Application Number:
  US09/032,098
• Time in Patent Office: 1,194 Days
• Field of Search: 348/308, 348/307, 348/300, 348/241, 348/243, 348/294, 348/296, 348/297, 348/362, 250/208.1, 250/214.A, 257/290, 257/291, 257/292
• US Class Current: 348/308
• CPC Class Codes: H01L 27/14609 Pixel-elements with integrated switching, control, storage or amplification elements scanning details of imagers (circuitry of solid-state image sensors H04N25/00); circuitry of imagers H04N25/70
• CPC Class Codes: H01L 27/14643 Photodiode arrays; MOS imagers
• CPC Class Codes: H04N 25/575 with a response composed of multiple slopes
• CPC Class Codes: H04N 25/616 involving a correlated sampling function, e.g. correlated double sampling [CDS] or triple sampling
• CPC Class Codes: H04N 25/65 applied to reset noise, e.g. KTC noise related to CMOS structures by techniques other than CDS
• CPC Class Codes: H04N 25/76 Addressed sensors, e.g. MOS or CMOS sensors
• CPC Class Codes: H04N 25/77 Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
• CPC Class Codes: H04N 25/771 comprising storage means other than floating diffusion

Abstract

A method for controlling a sensor to reduce reset noise is disclosed. The method including the steps of providing a reset command including a RESET signal and a first SAMPLE signal. The method also includes the steps of providing a read command including a first ADDRESS signal, a second SAMPLE signal, and a second ADDRESS signal. An apparatus including a system controller and a sensor controlled by the system controller is also disclosed. In one embodiment, the method and apparatus is provided for a sensor in a sensor array that is read-out in a pipelined fashion.

Claims

1. A method comprising:

asserting a sample signal and a reset signal to generate a reset voltage at a storage node of each photocell in a first group of photocells in an image sensor array; and

then

deasserting the reset signal prior to deasserting the sample signal so that the reset voltage is captured at the storage node; and

then

asserting a first address signal to read the captured reset voltage at the storage node;

waiting an integration period after deasserting the reset signal and before reading an exposed voltage at the storage node; and

generating a difference between the exposed voltage and the captured reset voltage.

2. The method of claim 1 further comprising asserting and deasserting the sample signal a second time to capture the exposed voltage.

3. The method of claim 1 wherein the reading of the captured reset voltage at the storage node includes sampling a voltage on a bitline to which the photocell is coupled.

4. The method of claim 1 wherein the sample signal and reset signal are asserted simultaneously.

5. The method of claim 1 further comprising

repeatedly performing the operations of claim 1 upon the image sensor array to read an image, in a pipelined manner.

6. An apparatus comprising:

a sensor array having a plurality of groups of photocells, each group of photocells being coupled to provide output voltages on a respective bitline, each photocell in a group having a reset device coupled to reset a photodetector in response to a reset signal being asserted, a sample device coupled to provide a low impedance path between the photodetector and a storage device, and a readout circuit coupled between the storage device and the respective bitline to provide an output voltage in response to an address signal being asserted; and

a controller coupled to control the sensor array by asserting a sample signal and a reset signal to generate a reset voltage at a storage node of each photocell in a first group of photocells in the sensor array; and

then

deasserting the reset signal prior to deasserting the sample signal so that the reset voltage is captured at the storage node; and

then

asserting a first address signal to read the captured reset voltage at the storage node, waiting an integration period after deasserting the reset signal and before reading an exposed voltage at the storage node, and generating a difference between the exposed voltage and the captured reset voltage.

7. The apparatus of claim 6 wherein each group of photocells forms a column and the first group forms a row.

8. The apparatus of claim 6 wherein the photodetector in each photocell includes a photodiode built using a MOS fabrication process.

9. The apparatus of claim 6 wherein each device is a single transistor.

10. The apparatus of claim 6 wherein the controller is to further control the sensor array by asserting and deasserting the sample signal a second time to capture the exposed voltage.

11. The apparatus of claim 6 wherein the controller is to further control the sensor array to repeatedly generate and read a reset voltage and an exposed voltage from the sensor array to read an image, in a pipelined manner.

12. The apparatus of claim 6 wherein the plurality of groups of photocells form substantially the entire sensor array, and the controller is further coupled to provide the same reset signal to each photocell in each group.

13. An article of manufacture comprising:

a machine-readable medium having instructions stored therein which, when executed by a processor, cause an imaging system to electronically capture an image by asserting a sample signal and a reset signal to generate a reset voltage at a storage node of each photocell in a first group of photocells in an image sensor array, and then deasserting the reset signal prior to deasserting the sample signal so that the reset voltage is captured at the storage node, and then asserting a first address signal to read the captured reset voltage at the storage node, waiting an integration period after deasserting the reset signal and before reading an exposed voltage at the storage node, and generating a difference between the exposed voltage and the captured reset voltage.

14. The article of manufacture of claim 13 wherein the machine readable medium includes further instructions which, when executed by the processor, cause the system to capture the image by asserting and deasserting the sample signal a second time to capture the exposed voltage.