Memory controller supporting redundant synchronous memories

• US 6,243,829 B1
• Filed: 05/27/1998
• Issued: 06/05/2001
• Est. Priority Date: 05/27/1998
• Status: Expired due to Term

• Current Assignee: Hewlett Packard Enterprise Development LP (Hewlett-Packard Enterprise Company)
• Original Assignee: Hewlett-Packard Company (HP Inc.)
• Inventors: Chan, Jong
• Primary Examiner(s): Lee, Thomas
• Assistant Examiner(s): NGUYEN, NGUYEN X
• Application Number:
  US09/085,204
• Time in Patent Office: 1,105 Days
• Field of Search: 714/5-7, 714/707, 714/10, 714/11, 710/110, 711/162, 711/172
• US Class Current: 714/5.11
• CPC Class Codes: G06F 11/2005 using redundant communication controllers
• CPC Class Codes: G06F 11/2097 maintaining the standby controller/processing unit updated initialisation or re-synchronisation thereof G06F11/1658 and subgroups

Abstract

A reliable fault-tolerant I/O controller supporting redundant synchronous memories is described. The I/O controller includes multiple I/O control logic units where each I/O control logic unit is in communication with a host server and external peripheral devices. Each I/O control logic unit includes a processor, a memory, and a memory controller. A master I/O control logic unit services I/O transactions from the host server and the external peripheral devices. A slave I/O control logic unit operates in a quiescent state until the master I/O control logic unit experiences a memory failure. At such time, the slave I/O control logic unit resumes operation of the I/O controller. In order to facilitate the switchover from the master I/O control logic unit to the slave I/O control logic unit, the master memory controller performs concurrent memory write operations in both the master and slave memories. The concurrent memory write operations ensure that the memories in both I/O control logic units are in a consistent state in order for the switchover to occur without loss of data.

Claims

1. An apparatus for controlling a data transfer between a data processor and a data unit, comprising:

a first control unit having a capability to control the data transfer between the data processor and the data unit, comprising;

a first memory controller generating a first address signal, a first control signal, and a first switch control signal;

a first memory device coupled to the first memory controller, the first memory device receives the first address signal, the first control signal, and a first data signal to perform a memory access; and

a first switch control unit that allows the first control unit to receive data values for the first address signal, the first control signal, and the first data signal, the first switch control unit coupled to the first switch control signal, and the first address signal, the first control signal, and the first data signal;

a second control unit that controls the data transfer between the data processor and the data unit, comprising;

a second memory controller generating a second address signal, a second control signal, and a second switch control signal;

a second memory device coupled to the second memory controller, the second memory device receives the second address signal, the second control signal, and a second data signal, to perform a memory access; and

a second signal switch control unit that allows the second control unit to transmit data values from the second address signal to the first address signal, from the second control signal to the first control signal, and from the second data signal to the first data signal, the second signal switch control unit coupled to the second switch control signal, the second address signal, the second control signal, and the second data signal.

2. The apparatus of claim 1,

the first switch control unit further including:

a first address switch coupled to the first address signal and the first switch control signal, the first address switch enables receipt of data values for the first address signal;

the second switch control unit further including;

a second address switch coupled to the second address signal, the second switch control signal, and the first address switch, the second address switch enables transmission of data values from the second address signal to the first address signal;

wherein the first switch control signal controls the first address switch to receive data values; and

wherein the second switch control signal controls the second address switch to transmit data values.

3. The apparatus of claim 2,

the first control unit further comprising:

a first address buffer that receives the first address signal and transmits the first address signal to the first memory device;

the second control unit further comprising;

a second address buffer that receives the second address signal and transmits the second address signal to the second memory device.

4. The apparatus of claim 3,

wherein the first address switch is positioned between the first memory controller and the first address buffer;

and

wherein the second address switch is positioned between the second memory controller and the second address buffer.

5. The apparatus of claim 1,

the first switch control unit further including:

a first data switch coupled to the first data signal and the first switch control signal, the first data switch enables receipt of data values for the first data signal;

the second switch control unit further including;

a second data switch coupled to the first data switch, a second data signal, and the second bus control signal, the second data switch enables transmission of data values from the second data signal to the first data signal;

wherein the first switch control signal controls the first data switch to receive data values; and

wherein the second switch control signal controls the second data switch to transmit data values.

6. The apparatus of claim 5,

the first control unit further comprising:

a first data buffer coupled to a first data signal, the first data buffer transmits the first data signal to the first memory device; and

the second control unit further comprising;

a second data buffer coupled to a second data signal, the second data buffer transmits the second data signal to the second memory device.

7. The apparatus of claim 6,

the first control unit further comprising:

a first bus coupled to the first memory controller and the first data buffer; and

wherein the first data buffer receives data values for the first data signal from the first bus;

the second control unit further comprising;

a second bus coupled to the second memory controller and the second data buffer; and

wherein the second data buffer receives data values for the second data signal from the second bus.

8. The apparatus of claim 6,

wherein the first data switch is positioned between the first data buffer and the first memory device;

and

wherein the second data switch is positioned between the second data buffer and the second memory device.

9. The apparatus of claim 1,

the first switch control unit further including:

a first control switch coupled to the first control signal and the first switch control signal, the first control switch enables receipt of data values for the first control signal;

the second switch control unit further including;

a second control switch coupled to the second control signal, the second switch control signal, and the first control switch, the second control switch enables transmission of data values from the second control signal to the first control signal;

wherein the first switch control signal controls the first control switch to receive data values; and

wherein the second switch control signal controls the second control switch to transmit data values.

10. The apparatus of claim 9,

the first control unit further comprising:

a first control buffer coupled to the first control signal and the first switch control signal, the first control buffer transmits the first control signal to the first memory device;

the second control unit further comprising;

a second control buffer coupled to the second control signal and the second bus control signal, the second control buffer transmits the second control signal to the second memory device.

11. The apparatus of claim 10,

wherein the first control switch is positioned between the first memory controller and the first control buffer;

and

wherein the second control switch is positioned between the second memory controller and the second control buffer.

12. The apparatus of claim 1, further comprising:

a first communication link coupled to the data processor and the first and second control units, the first communications link providing a data transfer between the data processor and the first and second control units; and

a second communication link coupled to the data unit and the first and second control units, the second communications link providing a data transfer between the data processor and the first and second control units.

13. The apparatus of claim 12,

wherein the first communication s link is a Fibre Channel;

and

wherein the second communications link is a SCSI Channel.

14. The apparatus of claim 1,

the second memory controller including a first logic unit that controls access to the first and second memory devices;

and

the first memory controller including a first logic unit that requests access to the first memory device from the second memory controller.

15. The apparatus of claim 1,

the first memory controller including a second logic unit that controls operation of the first memory controller, the second logic unit receiving a first fail signal indicating a memory failure to the first memory device, the second logic unit terminating operation of the first memory controller in response to the local fail signal;

and

the second memory controller including a second logic unit that controls operation of the second memory controller, the second logic unit receiving the first fail signal from the first memory controller, the second logic unit terminating access to the first memory device.

16. The apparatus of claim 15,

the second logic unit in the first memory controller receiving a reset signal and initializing operation of the first memory controller;

and

the second logic unit in the second memory controller receiving the reset signal and initializing operation of the second memory controller.

17. The apparatus of claim 1,

the second memory controller including a second logic unit that controls operation of the second memory controller, the second logic unit receiving a second fail signal indicating a failure to the second memory device, the second logic unit terminating operation of the second memory controller;

and

the first memory controller including a second logic unit that controls operation of the first memory controller, the second logic unit receiving the second fail signal, the second logic unit resuming control of the data transfer between the data processor and the data unit.