System for erasing a memory cell

  • US 6,246,611 B1
  • Filed: 02/28/2000
  • Issued: 06/12/2001
  • Est. Priority Date: 02/28/2000
  • Status: Expired due to Term
First Claim
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1. An erase control circuit that erases a memory cell, the control circuit comprising:

  • a plurality of memory cells that stores an erase signal value;

    a signal output circuit that is coupled to receive the erase signal value from the plurality of memory cells and that converts the erase signal value into an erase signal and outputs the erase signal to the memory cell; and

    a verification circuit, the verification circuit determining whether the memory cell successfully erased, wherein when the memory cell did not successfully erase, the signal output circuit increases the erase signal value.

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