System for erasing a memory cell

• US 6,246,611 B1
• Filed: 02/28/2000
• Issued: 06/12/2001
• Est. Priority Date: 02/28/2000
• Status: Expired due to Term

• Current Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Hong, James M., Le, Binh Quang, Chen, Pau-Ling, Pawletko, Joseph G.
• Primary Examiner(s): NGUYEN, TAN
• Application Number:
  US09/514,560
• Time in Patent Office: 470 Days
• Field of Search: 365/185.29, 365/185.22, 365/201, 365/185.09, 365/185.23
• US Class Current: 365/185.29
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/344 Arrangements for verifying correct erasure or for detecting overerased cells
• CPC Class Codes: G11C 16/3445 Circuits or methods to verify correct erasure of nonvolatile memory cells

Abstract

An erase control circuit erases a memory cell in accordance to an erase signal value that can be varied by a test equipment. The erase control circuit comprises a signal storage device, a signal output circuit, and a verification circuit. The signal storage device stores the erase signal value. A test equipment can be coupled to the signal storage device to write the programming signal value into the signal storage device. The signal output circuit is coupled to the signal storage device to receive the erase signal value. The signal output circuit converts the erase signal value into an erase signal and outputs the erase signal to the memory cell. The verification circuit determines whether the memory cell is successfully erased. If the memory cell is not successfully erased, the erase control circuit increases the erase signal value.

Claims

1. An erase control circuit that erases a memory cell, the control circuit comprising:

a plurality of memory cells that stores an erase signal value;

a signal output circuit that is coupled to receive the erase signal value from the plurality of memory cells and that converts the erase signal value into an erase signal and outputs the erase signal to the memory cell; and

a verification circuit, the verification circuit determining whether the memory cell successfully erased, wherein when the memory cell did not successfully erase, the signal output circuit increases the erase signal value.

2. The circuit of claim 1, wherein the signal output circuit converts the increased erase signal value into an increased erase signal and outputs the increased erase signal to the memory cell.

3. The circuit of claim 1, wherein the signal output circuit includes a counter circuit, the counter circuit storing the erase signal value.

4. The circuit of claim 3, wherein the plurality of memory cells is coupled to a test equipment and the test equipment stores the erase signal value into the plurality of memory cells.

5. The circuit of claim 3, wherein the counter circuit selectively increases the erase signal value.

6. The circuit of claim 1, wherein the signal output circuit increases the erase signal value in a non-linear order.

7. The circuit of claim 1, wherein the signal output circuit increases the erase signal value by a decreasing increment.

8. The circuit of claim 1, wherein the signal output circuit comprises:

an output terminal that provides the erase signal;

a first impedance element coupled to the output terminal;

a second impedance element coupled to the first impedance element, wherein the level of impedance of the second impedance element is controlled by the programming signal value; and

a comparator coupled to the first impedance element and the second impedance element, wherein the comparator controls the output terminal to provide the programming signal.

9. A method for erasing a memory cell, the method comprising the acts of:

storing an erase signal value in a plurality of memory cells;

loading the erase signal value into a counter circuit;

converting the erase signal value in the counter circuit into an erase signal;

applying the erase signal to the memory cell;

verifying the erase of the memory cell; and

if the memory cell has not successfully erased, increasing the erase signal value in the counter circuit.

10. The method of claim 9, further comprising the acts of

converting the increased erase signal value into an increased erase signal;

applying the increased erase signal to the memory cell; and

verifying the erase of the selected memory cell.

11. The method of claim 10, wherein the act of increasing further comprises increasing the erase signal value in a non-linear order.

12. An erase control circuit that erases a memory cell, the control circuit comprising:

a signal storage device that stores an erase signal value wherein the signal storage device is coupled to a test equipment and the test equipment stores the erase signal value into the signal storage device;

a signal output circuit that is coupled to receive the erase signal value from the signal storage device and that converts the erase signal value into an erase signal and outputs the erase signal to the memory cell, wherein the signal output circuit includes a counter circuit, the counter circuit storing the erase signal value; and

a verification circuit, the verification circuit determining whether the memory cell successfully erased, wherein if the memory cell did not successfully erase, the erase control circuit increases the erase signal value.

13. An erase control circuit that erases a memory cell, the control circuit comprising:

a signal storage device that stores an erase signal value;

a signal output circuit that is coupled to receive the erase signal value from the signal storage device and that converts the erase signal value into an erase signal and outputs the erase signal value to the memory cell, wherein the signal output circuit comprises a counter circuit, the counter circuit selectively increasing the erase signal value; and

a verification circuit, the verification circuit determining whether the memory cell successfully erased, wherein if the memory cell did not successfully erase, the erase control circuit increases the erase signal value.

14. An erase control circuit that erases a memory cell, the control circuit comprising:

a signal storage device that stores an erase signal value;

a signal output circuit that is coupled to receive the erase signal value from the signal storage device and that converts the erase signal value into an erase signal and outputs the erase signal value to the memory cell, wherein the signal output circuit comprises;

an output terminal that provides the erase signal;

a first impedance element coupled to the output terminal;

a second impedance element coupled to the first impedance element, wherein the level of impedance of the second impedance element is controlled by the erase signal value; and

a comparator coupled to the first impedance element and the second impedance element, wherein the comparator controls the output terminal to provide the erase signal; and

a verification circuit, the verification circuit determining whether the memory cell successfully erased, wherein if the memory cell did not successfully erase, the erase control circuit increases the erase signal value.