Floating back gate electrically erasable programmable read-only memory (EEPROM)
First Claim
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1. A method for producing a floating gate on the back of a transistor channel, comprising:
- forming a buried oxide on a conducting substrate;
forming a back-plane over the buried oxide;
forming a back oxide over the back-plane;
forming a silicon layer over the back oxide, the silicon layer having a thickness substantially comparable to that of said back-plane, through which charge gets injected into the back-plane; and
patterning a silicon region for the memory to form a source, drain and channel region of the memory and a floating gate region, and filling, with an insulator, said source, drain and channel region and the floating gate region;
wherein the back-plane is formed of a conductive high electron affinity material which does not substantially interact with the back-oxide and the buried oxide, wherein said back-plane is formed of any of W, WN, TiN, and alloys thereof.
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Abstract
A semiconductor memory and a method of producing the memory, includes a transistor including a first gate having an oxide, and a channel, and a back-plane including a second gate and an oxide thereover, the second gate formed opposite to the channel of the transistor, the second gate including a floating gate, wherein a thickness of the oxide of the back-plane is separately scalable from an oxide of the first gate of the transistor.
79 Citations
12 Claims
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1. A method for producing a floating gate on the back of a transistor channel, comprising:
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forming a buried oxide on a conducting substrate;
forming a back-plane over the buried oxide;
forming a back oxide over the back-plane;
forming a silicon layer over the back oxide, the silicon layer having a thickness substantially comparable to that of said back-plane, through which charge gets injected into the back-plane; and
patterning a silicon region for the memory to form a source, drain and channel region of the memory and a floating gate region, and filling, with an insulator, said source, drain and channel region and the floating gate region;
wherein the back-plane is formed of a conductive high electron affinity material which does not substantially interact with the back-oxide and the buried oxide, wherein said back-plane is formed of any of W, WN, TiN, and alloys thereof. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
growing a control oxide on the substrate.
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3. The method according to claim 2, further comprising:
depositing a gate material comprising one of polysilicon and a non-reactive metal.
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4. The method according to claim 3, further comprising:
patterning a gate from said gate material, and growing a side-wall oxide, and forming a doped link region by ion implantation and annealing.
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5. The method according to claim 4, further comprising:
depositing an insulating oxide to form a side-wall, and performing a doping by one of implantation and annealing and epitaxy, thereby to form source and drain regions.
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6. The method according to claim 5, further comprising:
removing residual oxide on the source, gate, and drain region and performing silicidation, thereby to form contacts of said memory.
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7. The method according to claim 6, further comprising:
forming logic transistors, by etching to the back-plane and forming contacts thereon.
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8. The method according to claim 7, wherein said transistor is selectively operable as a dual-gate device and as where the back-plane controls the threshold voltage of the transistor.
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9. The method according to claim 8, wherein said memory comprises an 8-bit NAND-architected cell structure including select transistors having a back-plane gate externally available.
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10. The method according to claim 8, wherein said memory comprises a NOR-architected cell structure.
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11. A method for producing a floating gate on the back of a transistor channel, comprising:
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forming a buried oxide on a conducting substrate;
forming a back-plane over the buried oxide;
forming a back oxide over the back-plane; and
forming a silicon layer over the back oxide, the silicon layer having a thickness substantially comparable to that of said back-plane, through which charge gets injected into the back-plane, wherein a floating gate is formed from said back-plane and a control gate is formed from said silicon layer, and wherein in a scaling of a size of said memory, a thickness of the floating gate is decoupled from a thickness of the control gate. - View Dependent Claims (12)
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Specification