Floating back gate electrically erasable programmable read-only memory (EEPROM)

• US 6,248,626 B1
• Filed: 07/17/1998
• Issued: 06/19/2001
• Est. Priority Date: 05/04/1998
• Status: Expired due to Fees

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Tiwari, Sandip, Kumar, Arvind
• Primary Examiner(s): Wilczewski, Mary
• Assistant Examiner(s): GOODWIN, DAVID J
• Application Number:
  US09/116,987
• Time in Patent Office: 1,068 Days
• Field of Search: 438/455, 438/456, 438/457, 438/406, 438/257, 438/217, 438/276, 438/259, 438/589, 438/593, 438/594, 257/295, 257/297, 257/300, 257/302, 257/303, 257/306
• US Class Current: 438/257
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/42336 with one gate at least partly formed in a trench
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/7883 charging by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling
• CPC Class Codes: H01L 29/7885 Hot carrier injection from the channel
• CPC Class Codes: H10B 41/10 characterised by the top-view layout
• CPC Class Codes: H10B 41/30 characterised by the memory core region

Abstract

A semiconductor memory and a method of producing the memory, includes a transistor including a first gate having an oxide, and a channel, and a back-plane including a second gate and an oxide thereover, the second gate formed opposite to the channel of the transistor, the second gate including a floating gate, wherein a thickness of the oxide of the back-plane is separately scalable from an oxide of the first gate of the transistor.

Claims

1. A method for producing a floating gate on the back of a transistor channel, comprising:

forming a buried oxide on a conducting substrate;

forming a back-plane over the buried oxide;

forming a back oxide over the back-plane;

forming a silicon layer over the back oxide, the silicon layer having a thickness substantially comparable to that of said back-plane, through which charge gets injected into the back-plane; and

patterning a silicon region for the memory to form a source, drain and channel region of the memory and a floating gate region, and filling, with an insulator, said source, drain and channel region and the floating gate region;

wherein the back-plane is formed of a conductive high electron affinity material which does not substantially interact with the back-oxide and the buried oxide,

wherein said back-plane is formed of any of W, WN, TiN, and alloys thereof.

2. The method according to claim 1, further comprising:

growing a control oxide on the substrate.

3. The method according to claim 2, further comprising:

depositing a gate material comprising one of polysilicon and a non-reactive metal.

4. The method according to claim 3, further comprising:

patterning a gate from said gate material, and growing a side-wall oxide, and forming a doped link region by ion implantation and annealing.

5. The method according to claim 4, further comprising:

depositing an insulating oxide to form a side-wall, and performing a doping by one of implantation and annealing and epitaxy, thereby to form source and drain regions.

6. The method according to claim 5, further comprising:

removing residual oxide on the source, gate, and drain region and performing silicidation, thereby to form contacts of said memory.

7. The method according to claim 6, further comprising:

forming logic transistors, by etching to the back-plane and forming contacts thereon.

8. The method according to claim 7, wherein said transistor is selectively operable as a dual-gate device and as where the back-plane controls the threshold voltage of the transistor.

9. The method according to claim 8, wherein said memory comprises an 8-bit NAND-architected cell structure including select transistors having a back-plane gate externally available.

10. The method according to claim 8, wherein said memory comprises a NOR-architected cell structure.

11. A method for producing a floating gate on the back of a transistor channel, comprising:

forming a buried oxide on a conducting substrate;

forming a back-plane over the buried oxide;

forming a back oxide over the back-plane; and

forming a silicon layer over the back oxide, the silicon layer having a thickness substantially comparable to that of said back-plane, through which charge gets injected into the back-plane,

wherein a floating gate is formed from said back-plane and a control gate is formed from said silicon layer, and

wherein in a scaling of a size of said memory, a thickness of the floating gate is decoupled from a thickness of the control gate.

12. The method according to claim 11, wherein said floating gate has a predetermined size for discrete electron sensitivity.