Partially depleted SOI device having a dedicated single body bias means

• US 6,249,027 B1
• Filed: 06/08/1998
• Issued: 06/19/2001
• Est. Priority Date: 06/08/1998
• Status: Expired due to Term

• Current Assignee: Oracle America, Inc. (Oracle Corporation)
• Original Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Inventors: Burr, James B.
• Primary Examiner(s): Abraham, Fetsum
• Application Number:
  US09/092,974
• Time in Patent Office: 1,107 Days
• Field of Search: 257/347, 257/355, 257/59, 257/369, 257/351, 257/348, 257/349, 257/350, 257/328
• US Class Current: 257/350
• CPC Class Codes: H01L 29/78609 for preventing leakage current H01L29/78618 takes precedence
• CPC Class Codes: H01L 29/78615 with a body contact

Abstract

A conductive body contact or layer is embedded in the bulk region of a partially depleted SOI device. The contact or layer is connected to the output of a bias voltage generator which generates a substrate bias voltage. The substrate bias voltage is routed to the bulk by way of the contact or layer to bias the threshold voltage of the partially depleted SOI device.

Claims

1. A semiconductor device comprising:

a partially depleted SOI device including (a) a semiconductor substrate, (b) an insulating layer formed along a surface of said semiconductor substrate, and (c) a transistor formed on said insulating layer such that said insulating layer is interposed between said transistor and said semiconductor substrate, said transistor including source and drain regions of a first conductivity type formed on said insulating layer, an intermediate region of a second conductivity type formed on said insulating layer and between said source and drain regions, and a gate electrode aligned over said intermediate region, wherein said intermediate region includes a depletion region defining a channel of said transistor and a non-depletion region defining a bulk of said transistor;

first, second, third and fourth terminals electrically coupled to said source region, said drain region, said gate electrode and said bulk, respectively; and

,

a bias voltage generator, said bias voltage generator selectively supplying a single selected bias voltage directly to said fourth terminal wherein said fourth terminal is isolated from said first through third terminals and further wherein;

said bias voltage is supplied directly to said fourth terminal and said bulk of said transistor to tune a threshold voltage of said transistor of said partially depleted SOI device to account for variations in the processing of said partially depleted SOI device, the temperature of said partially depleted SOI device and the activity of said partially depleted SOI device.

2. A semiconductor device as claimed in claim 1, further comprising a conductive body contact embedded in said bulk and connected to said fourth terminal.

3. A semiconductor device as claimed in claim 2, wherein said partially depleted SOI device is located on a semiconductor chip, and wherein said bias voltage generator is located off said semiconductor chip.

4. A semiconductor device as claimed in claim 2, further comprising a plurality of said partially depleted SOI devices on a semiconductor chip, wherein said plurality of partially depleted SOI devices are functionally divided on said semiconductor chip to define a plurality of domains on said semiconductor chip, and wherein said semiconductor device further includes a plurality of said bias voltage generators for said respective domains.

5. A semiconductor device as claimed in claim 4, wherein at least one of said plurality of bias voltage generators is located off said semiconductor chip.

6. A semiconductor device as claimed in claim 1, further comprising a conductive layer of the second conductivity type contained within said bulk and connected to said fourth terminal.

7. A semiconductor device as claimed in claim 6, wherein said partially depleted SOI device is located on a semiconductor chip, and wherein said bias voltage generator is located off said semiconductor chip.

8. A semiconductor device as claimed in claim 6, further comprising a plurality of said partially depleted SOI devices on a semiconductor chip, wherein said plurality of partially depleted SOI devices are functionally divided on said semiconductor chip to define a plurality of domains on said semiconductor chip, and wherein said semiconductor device further includes a plurality of said bias voltage generators for said respective domains.

9. A semiconductor device as claimed in claim 8, wherein at least one of said plurality of bias voltage generators is located off said semiconductor chip.

10. A semiconductor device as claimed in claim 1, wherein said partially depleted SOI device is located on a semiconductor chip, and wherein said bias voltage generator is located off said semiconductor chip.

11. A semiconductor device as claimed in claim 1, further comprising a plurality of said partially depleted SOI devices on a semiconductor chip, wherein said plurality of partially depleted SOI devices are functionally divided on said semiconductor chip to define a plurality of domains on said semiconductor chip, and wherein said semiconductor device further includes a plurality of said bias voltage generators for said respective domains.

12. A semiconductor device as claimed in claim 11, wherein at least one of said plurality of bias voltage generators is located off said semiconductor chip.