Full frame electronic shutter camera

• US 6,259,478 B1
• Filed: 04/01/1994
• Issued: 07/10/2001
• Est. Priority Date: 04/01/1994
• Status: Expired due to Term

• Current Assignee: Pulnix America Incorporated (JAI A/S)
• Original Assignee: Pulnix America Incorporated (JAI A/S)
• Inventors: Hori, Toshikazu
• Primary Examiner(s): Garber, Wendy
• Assistant Examiner(s): CHRISTENSEN, ANDREW BRUCE
• Application Number:
  US08/221,721
• Time in Patent Office: 2,657 Days
• Field of Search: 348/296, 348/88, 348/304, 348/132, 348/297, 348/125, 348/231, 348/305-314, 250/208.1
• US Class Current: 348/296
• CPC Class Codes: H04N 25/53 Control of the integration time
• CPC Class Codes: H04N 25/622 by controlling anti-blooming drains
• CPC Class Codes: H04N 25/71 Charge-coupled device [CCD] sensors; Charge-transfer registers specially adapted for CCD sensors

Abstract

An electronic shutter camera with full frame resolution employs a progressively scanned interline transfer charge coupled device for generating full frame images of objects moving past an observation point either asynchronously in response to an external trigger signal or synchronously with internal timing. The image charges accumulated on the pixel regions of the CCD are discharged once per frame time, and the pixel regions are also initially discharged prior to the beginning of an image charge integration period to remove noise. A special double pulse mode enables the shutter speed to be specified by externally generated double trigger pulses, with the spacing between pulses specifying the desired shutter time. Manual selection of a wide range of shutter speeds is also provided. Each image frame is stored in a digital memory and is output as either interlaced or non-interlaced analog or digital video.

Claims

1. An electronic shutter camera with full frame resolution, said camera comprising:

a progressive scanning interline transfer charge coupled device (CCD) for imaging a frame of information;

timing means for generating electronic shutter signals for controlling the scanning and charge transfer rate for said CCD;

sync generator means for generating video timing signals;

control means for resetting said timing means and said sync generator means, said control means including means for selecting an internal reset mode and an external reset mode of operation for said timing means and said sync generator means, said control means further including means responsive to an externally supplied asynchronous reset signal for resetting said timing means and said sync generator means;

digital image generating means coupled to said CCD for generating multiple bit digital image signals;

individual memory means coupled to said digital image generating means for storing a full frame multi-bit digital image; and

means for converting said full frame multi-bit digital image to video signals having a selected format.

2. The invention of claim 1 wherein said CCD has a vertical overflow drain structure.

3. The invention of claim 1 wherein said control means includes manually selectable means for specifying the shutter speed.

4. The invention of claim 1 wherein said control means includes means responsive to a pair of externally supplied pulses for selecting the shutter speed in accordance with the time separation between preselected portions of said pair of externally supplied pulses.

5. The invention of claim 1 wherein said converting means includes means for outputting said frame image as interlaced successive fields of video information.

6. The invention of claim 1 wherein said converting means includes means for outputting said frame image as a non-interlaced frame of video information.

7. The invention of claim 1 wherein said individual memory means comprises a digital storage device having a memory capacity of at least one frame of information, and an analog to digital converter coupled between said CCD and said digital storage device for converting CCD analog output signals to digital equivalent signals.

8. The invention of claim 7 wherein said converting means includes a digital to analog converter coupled to said digital storage device for converting digital equivalent signals stored in said digital storage device to analog video output signals.

9. The invention of claim 7 wherein said converting means includes means for accessing said digital equivalent signals in said digital storage device in a pixel sequential alternate line sequential order so that said analog video output signals are output in interlaced format as odd and even fields.

10. The invention of claim 7 wherein said converting means includes means for accessing said digital equivalent signals in said digital storage device in pixel sequential line sequential order so that said analog video output signals are output in non-interlaced format.

11. An electronic shutter camera with full-frame resolution, said camera comprising:

a progressive scanning interline transfer charge coupled device (CCD) for imaging a frame of information;

timing means for generating electronic shutter signals for controlling the scanning and charge transfer rate for said CCD;

sync generator means for generating video timing signals;

control means for resetting said timing means and said sync generator means;

digital image generating means coupled to said CCD for generating multiple bit digital image signals;

individual memory means coupled to said digital image generating means for storing a full-frame multi-bit digital image; and

means for converting a full-frame multi-bit digital image to video signals having a selected format,

said timing means, said sync generator means, said control means, said memory means and said converting means all being located within the camera.

12. An electronic shutter camera with full-frame resolution, said camera comprising:

a progressive scanning interline transfer charge coupled device (CCD) for imaging a frame of information;

timing means for generating electronic shutter signals for controlling the scanning and charge transfer rate for said CCD;

sync generator means for generating video timing signals;

control means for resetting said timing means and said sync generator means in response to the receipt of an externally supplied asynchronous reset signal, said control means including means responsive to a pair of externally supplied pulses for selecting the shutter speed in accordance with the time separation between pre-selected portions of said pair of externally supplied pulses; and

means for converting individual lines of said frame of information to video signals having a selected format.

13. The invention of claim 12 wherein said converting means includes means for outputting said individual lines of said frame of information to an interlaced video format.

14. The invention of claim 12 wherein said converting means includes means for outputting said individual lines of said frame of information to a non-interlaced video format.

15. The invention of claim 12 further including digital image generating means coupled to said CCD for generating multiple bit digital image signals;

and wherein said converting means includes individual memory means coupled to said digital image generating means for storing a full-frame multi-bit digital image.

16. The invention of claim 15 wherein said memory means comprises a digital storage device having a memory capacity of at least one frame of information, and wherein said digital image generating means includes an analog to digital converter coupled between said CCD and said digital storage device for converting CCD analog output signals to digital equivalent signals.

17. The invention of the claim 16 wherein said converting means includes a digital to analog converter coupled to said digital storage device for converting digital equivalent signals stored in said digital storage device to analog video output signals.

18. The invention of claim 16 wherein said converting means includes means for accessing said digital equivalent signals in said digital storage device in a pixel sequential alternative line sequential order so that said analog video output signals are output in interlaced format as odd and even fields.

19. The invention of claim 16 wherein said converting means includes means for accessing said digital equivalent signals in said digital storage device in pixel sequential line sequential order so that said analog video output signals are output in non-interlaced format.