Single integrated circuit embodying a risc processor and a digital signal processor

• US 6,260,088 B1
• Filed: 03/03/2000
• Issued: 07/10/2001
• Est. Priority Date: 11/17/1989
• Status: Expired due to Fees

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Guttag, Karl Marion, Balmer, Keith, Gove, Robert J., Ing-Simmons, Nicholas Kerin
• Primary Examiner(s): Etienne, Ario
• Application Number:
  US09/517,990
• Time in Patent Office: 494 Days
• Field of Search: 710/100, 710/101, 710/131, 710/132, 712/20, 712/21, 712/22, 712/10, 712/28, 712/34, 712/35, 712/41, 712/43
• US Class Current: 710/100
• CPC Class Codes: G06F 15/17375 One dimensional, e.g. linear array, ring

Abstract

A single integrated circuit includes first and second data processors operating on different instruction sets independently operating on disjoint programs and data. The single integrated circuit preferably includes an external interface, a shared data transfer controller and shared memory divided into plural independently accessible memory banks. The two data processors are preferably a digital signal processor (DSP) and a reduced instruction set computer (RISC) processor. The DSP and RISC processors are suitably programmed to perform differing aspects of computer image processing.

Claims

1. A single integrated circuit comprising:

a first data processor having a first set of data processing structures capable of data processing according to a first instruction set; and

a second data processor having a second set of data processing structures different from said first set of data processing structures capable of data processing according to a second instruction set different from said first instruction set;

wherein said first and second data processors are capable of independent operations on disjoint instructions and data sets.

2. The single integrated circuit of claim 1, further comprising:

an external interface connected to said first and second data processors and connectable to devices external to said single integrated circuit.

3. The single integrated circuit of claim 2, further comprising:

a transfer controller connecting said first and second data processors to said external interface, said transfer controller capable of transferring data from a selected one of said first and second data processors to said external interface and from said external interface to a selected one of said first and second data processors.

4. The single integrated circuit of claim 1, further comprising:

a first read/write memory connected to said first data processor, whereby said first processor is capable of reading from or writing to said first read/write memory; and

a second read/write memory connected to said second data processor, whereby said second data processor is capable of reading from or writing to said second read/write memory.

5. The single integrated circuit of claim 1, further comprising:

a read/write memory connected to said first and second data processors, whereby said first processor is capable of reading from or writing to said read/write memory and said second processor is capable of reading from or writing to said read/write memory.

6. The single integrated circuit of claim 5, wherein:

said read/write memory consists of a plurality of memory banks, each memory bank individually accessible by said first and said second data processors.

7. The single integrated circuit of claim 6, wherein:

said first and second data processors independently access respective ones of said plurality of memory banks.

8. The single integrated circuit of claim 7, wherein:

said first data processor has priority over said second data processor if both said first and second data processors simultaneously attempt to access the same one of said plurality of memory banks.

9. The single integrated circuit of claim 6, wherein:

each of said plurality of memory banks is assigned a unique memory number;

said single integrated circuit further includes;

an address comparator connected to each of said first and second data processors and to a corresponding one of said plurality of memory banks, each address comparator granting a selected one of said first and second data processors access to said corresponding one of said plurality of memory banks if a predetermined subset of bits of an address received from said selected one of said first and second data processors matches said memory number assigned to said corresponding one of said plurality of memory banks.

10. The single integrated circuit of claim 1, further comprising:

a first memory bank connected to said first data processor storing instructions in said first instruction set; and

a second memory bank connected to said second data processor storing instructions in said second instruction set; and

wherein said first data processor operates in accordance with instructions in said first instruction set recalled from said first memory bank and said second data processor operates in accordance with instructions in said second instruction set recalled from said second memory bank.

11. The single integrated circuit of claim 10, further comprising:

a plurality of third memory banks, each third memory bank connected to said first and second data processors permitting a selected one of said first and second data processor to read data from or write data to said third memory bank.

12. The single integrated circuit of claim 1, wherein:

said second data processor includes an interrupt input for interrupting a current operation and causing execution of a priority operation; and

said first data processor is connected to said interrupt input of said second data processor, whereby said first data processor may perform an operation causing an interrupt of said second data processor.

13. The single integrated circuit of claim 1, wherein:

said first data processor is a digital signal processor (DSP); and

said second data processor is a reduced instruction set computer (RISC) processor.

14. The single integrated circuit of claim 13, wherein:

said digital signal processor includes a single instruction cycle integer multiplier unit.

15. The single integrated circuit of claim 13, wherein:

said reduced instruction set computer processor includes a floating point execution unit.

16. A method of image identification comprising the steps of:

disposing on a single integrated circuit a digital signal processor having a first set of data processing structures capable of data processing according to a first instruction set, a reduced instruction set computer processor having a second set of data processing structures different from said first set of data processing structures capable of data processing according to a second instruction set different from said first instruction set, an external interface connected to said first and second data processors and connectable to devices external to said single integrated circuit, wherein said first and second data processors are capable of independent operations on disjoint instructions and data sets;

connecting a memory to said external interface; and

disposing in said memory a first set of instructions in said first instruction set and a second set of instructions in said second instruction set, said first set of instructions controlling operation of said digital signal processor and said second set of instructions in said second instruction set controlling operation of said reduced instruction set computer processor cooperatively to perform image recognition.

17. The method of image identification of claim 16, wherein:

said step of disposing in said memory said first set of instructions in said first instruction set includes instructions controlling said digital signal processor to perform image decompression.

18. The method of image identification of claim 16, wherein:

said step of disposing in said memory said first set of instructions in said first instruction set includes instructions controlling said digital signal processor to perform image compression.

19. The method of image identification of claim 16, wherein:

said step of disposing in said memory said first set of instructions in said first instruction set includes instructions controlling said digital signal processor to perform edge extraction.

20. The method of image identification of claim 16, wherein:

said step of disposing in said memory said first set of instructions in said first instruction set includes instructions controlling said digital signal processor to perform line linkage.

21. The method of image identification of claim 16, wherein:

said step of disposing in said memory said first set of instructions in said first instruction set includes instructions controlling said digital signal processor to perform corner and vertex recognition.

22. The method of image identification of claim 16, wherein:

said step of disposing in said memory said first set of instructions in said first instruction set includes instructions controlling said digital signal processor to perform pixel intensity histogram determination.

23. The method of image identification of claim 16, wherein:

said step of disposing in said memory said first set of instructions in said first instruction set includes instructions controlling said digital signal processor to perform image segmentation.

24. The method of image identification of claim 16, wherein:

said step of disposing in said memory said second set of instructions in said second instruction set includes instructions controlling said reduced instruction set computer processor to perform template matching.

25. The method of image identification of claim 16, wherein:

said step of disposing in said memory said second set of instructions in said second instruction set includes instructions controlling said reduced instruction set computer processor to perform object identification.

26. A method of image creation comprising the steps of:

disposing on a single integrated circuit a digital signal processor having a first set of data processing structures capable of data processing according to a first instruction set, a reduced instruction set computer processor having a second set of data processing structures different from said first set of data processing structures capable of data processing according to a second instruction set different from said first instruction set, an external interface connected to said first and second data processors and connectable to devices external to said single integrated circuit, wherein said first and second data processors are capable of independent operations on disjoint instructions and data sets;

connecting a memory to said external interface; and

disposing in said memory a first set of instructions in said first instruction set and a second set of instructions in said second instruction set, said first set of instructions controlling operation of said digital signal processor and said second set of instructions in said second instruction set controlling operation of said reduced instruction set computer processor cooperatively to perform image creation.

27. The method of image creation of claim 26, wherein:

said step of disposing in said memory said second set of instructions in said second instruction set includes instructions controlling said reduced instruction set computer processor to perform geometric modeling.

28. The method of image creation of claim 26, wherein:

said step of disposing in said memory said second set of instructions in said second instruction set includes instructions controlling said reduced instruction set computer processor to perform two dimensional transformation of a geometric model.

29. The method of image creation of claim 26, wherein:

said step of disposing in said memory said second set of instructions in said second instruction set includes instructions controlling said reduced instruction set computer processor to perform three dimensional transformation of a geometric model.

30. The method of image creation of claim 26, wherein:

said step of disposing in said memory said second set of instructions in said second instruction set includes instructions controlling said reduced instruction set computer processor to perform object visibility determination.

31. The method of image creation of claim 26, wherein:

said step of disposing in said memory said second set of instructions in said second instruction set includes instructions controlling said reduced instruction set computer processor to perform object shading.

32. The method of image creation of claim 26, wherein:

said step of disposing in said memory said first set of instructions in said first instruction set includes instructions controlling said digital signal processor to perform clipping of objects based upon a predetermined view.

33. The method of image creation of claim 26, wherein:

said step of disposing in said memory said first set of instructions in said first instruction set includes instructions controlling said digital signal processor to perform font compilation.

34. The method of image creation of claim 26, wherein:

said step of disposing in said memory said first set of instructions in said first instruction set includes instructions controlling said digital signal processor to perform drawing to pixel map memory.

35. A method of data processing comprising the steps of:

disposing on a single integrated circuit a digital signal processor having a first set of data processing structures capable of data processing according to a first instruction set, a reduced instruction set computer processor having a second set of data processing structures different from said first set of data processing structures capable of data processing according to a second instruction set different from said first instruction set, an external interface connected to said first and second data processors and connectable to devices external to said single integrated circuit, wherein said first and second data processors are capable of independent operations on disjoint instructions and data sets;

connecting a memory to said external interface; and

disposing in said memory a first set of instructions in said first instruction set and a second set of instructions in said second instruction set, said first set of instructions controlling operation of said digital signal processor to perform two dimensional array processing and said second set of instructions in said second instruction set controlling operation of said reduced instruction set computer processor to perform information and/or display list processing.

36. A single integrated circuit comprising:

a first data processor having a first set of data processing structures capable of data processing according to a first instruction set;

a second data processor having a second set of data processing structures different from said first set of data processing structures capable of data processing according to a second instruction set different from said first instruction set;

a first memory bank connected to said first data processor storing instructions in said first instruction set;

a second memory bank connected to said second data processor storing instructions in said second instruction set;

said first and second memory banks being configured as respective first and second instruction caches;

said first data processor further including;

a first program counter storing an address of a next instruction in said first instruction set to be executed by said first data processor,

a first instruction cache logic circuit connected to said program counter and said first instruction cache for determining if the instruction corresponding to the address stored in said first program counter is stored in said first instruction cache;

said second data processor further including;

a second program counter storing an address of a next instruction in said second instruction set to be executed by said second data processor,

a second instruction cache logic circuit connected to said second program counter and said second instruction cache for determining if the instruction corresponding to the address stored in said second program counter is stored in said second instruction cache;

an external interface connectable to devices external to said single integrated circuit; and

a transfer controller connected to said first and second data processors, said external interface and said first and second memory banks, said transfer controller transferring an instruction via said external interface corresponding to the address stored in said first program counter from a device external to said single integrated circuit to said first instruction cache if said first instruction cache logic circuit determines said instruction is not stored in said first instruction cache, and said transfer controller transferring an instruction via said external interface corresponding to the address stored in said second program counter from a device external to said single integrated circuit to said second instruction cache if said second instruction cache logic circuit determines the instruction is not stored in said second instruction cache;

wherein said first and second data processors are capable of independent operations on disjoint instructions and data sets, said first data processor operating in accordance with instructions in said first instruction set recalled from said first memory bank and said second data processor operating in accordance with instructions in said second instruction set recalled from said second memory bank.

37. A single integrated circuit comprising:

a first data processor having a first set of data processing structures capable of data processing according to a first instruction set;

a second data processor having a second set of data processing structures different from said first set of data processing structures capable of data processing according to a second instruction set different from said first instruction set;

a first memory bank connected to said first data processor storing instructions in said first instruction set;

a second memory bank connected to said second data processor storing instructions in said second instruction set;

a plurality of third memory banks, each third memory bank connected to said first and second data processors permitting a selected one of said first and second data processor to read data from or write data to said third memory bank;

at least a fourth memory bank and a fifth memory of said plurality of third memory banks being configured as respective first and second data caches;

said first data processor further including;

a first address register storing an address of a next data to be read or written by said first data processor,

a first data cache logic circuit connected to said first address register and said first data cache for determining if the data corresponding to the address stored in said first address register is stored in said first data cache;

said second data processor further including;

a second address register storing an address of a next data to be read or written by said second data processor,

a second data cache logic circuit connected to said second address register and said second data cache for determining if the data corresponding to the address stored in said second address register is stored in said second data cache;

an external interface connectable to devices external to said single integrated circuit; and

a transfer controller connected to said first and second data caches and to said external interface, said transfer controller transferring data via said external interface corresponding to the address stored in said first address register from a device external to said single integrated circuit to said first data cache if said first data cache logic circuit determines said data is not stored in said first data cache upon a data read, said transfer controller transferring data via said external interface corresponding to the address stored in said first address register from said first data cache to a device external to said single integrated circuit if said first data cache logic circuit determines said data is not stored in said first data cache upon a data write, said transfer controller transferring data via said external interface corresponding to the address stored in said second address register from a device external to said single integrated circuit to said second data cache if said second data cache logic circuit determines said data is not stored in said second data cache upon a data read, and said transfer controller transferring data via said external interface corresponding to the address stored in said second address register from said second data cache to a device external to said single integrated circuit if said second data cache logic circuit determines said data is not stored in said second data cache upon a data write;

where said first and second data processors are capable of independent operations on disjoint instructions and data sets, said first data processor operates in accordance with instructions in said first instruction set recalled from said first memory bank and said second data processor operates in accordance with instructions in said second instruction set recalled from said second memory bank.