Computer system capable of controlling the power supplied to specific modules

• US 6,260,151 B1
• Filed: 03/12/1998
• Issued: 07/10/2001
• Est. Priority Date: 03/14/1997
• Status: Expired due to Fees

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Omizo, Takashi, Muratake, Shigeki, Okazaki, Yoshihiko
• Primary Examiner(s): Beausoleil, Robert
• Assistant Examiner(s): PHAN, RAYMOND NGAN
• Application Number:
  US09/038,628
• Time in Patent Office: 1,216 Days
• Field of Search: 713/800, 713/310, 713/320, 713/322, 713/323, 713/324, 713/330, 713/340, 711/105-107
• US Class Current: 713/324
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3237 by disabling clock generation or distribution
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: G06F 1/325 Power saving in peripheral device
• CPC Class Codes: G06F 1/3253 Power saving in bus
• CPC Class Codes: G06F 1/3287 by switching off individual functional units in the computer system
• CPC Class Codes: G06F 1/3296 by lowering the supply or operating voltage
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

In a computer system, a control signal line directly connecting a processor to a power sequence controller is provided and a PSC interface for exchanging a control signal with the power sequence controller is built in the processor. When all the devices connected to a specific IO bus have been out of use for a long time, the processor transmits a control signal to stop the supply of power to the IO bus to the power sequence controller. This stops power from being supplied to not only the devices connected to the IO bus but also the IO bus. As a result, the unnecessarily consumed power in the computer system is reduced remarkably.

Claims

1. A computer system comprising:

a processor containing at least one power-consuming module including a floating-point arithmetic module;

control means for controlling supply and cut of a clock signal supplied to at least one of said power-consuming modules;

clock conversion means, provided between an oscillation circuit and at least one of said power-consuming modules for converting a frequency of an inputted clock stepwise in a range from an original frequency to a stopping state, wherein when the supply of the clock signal to at least one of said power-consuming modules is stopped. transmitting a control signal to said clock conversion device such that the frequency of the clock is converted stepwise in a direction of changing from the original frequency toward the stopping state. and when the supply of the clock signal to at least one of said power-consuming modules is resumed. transmitting a control signal to said clock conversion device such that the frequency of the clock is converted stepwise in a direction of changing from the stopping state toward the original frequency,

sensing means for sensing a remaining capacity of a battery serving as a power supply, wherein said control means includes means for adjusting a frequency of the clock supplied to said at least one of power-consuming modules in accordance with the remaining capacity of the battery sensed by said sensing means.

2. A computer system comprising:

a processor containing power-consuming modules including a floating point arithmetic module;

control means for controlling supply and cut of a clock signal supplied to at least one of said power-consuming modules; and

sensing means for sensing a remaining capacity of a battery serving as a power supply,

wherein said control means includes means for adjusting a frequency of the clock signal supplied to at least one of said power-consuming modules in accordance with the remaining capacity of the battery sensed by said sensing means.