Pipeline processing machine with interactive stages operable in response to tokens and system and methods relating thereto

• US 6,263,422 B1
• Filed: 06/07/1995
• Issued: 07/17/2001
• Est. Priority Date: 06/30/1992
• Status: Expired due to Term

• Current Assignee: Chartoleaux KG LLC (Intellectual Ventures LLC)
• Original Assignee: Discovision Associates (Pioneer Corporation)
• Inventors: Wise, Adrian P., Robbins, William P., Sotheran, Martin W.
• Primary Examiner(s): Follansbee, John A.
• Application Number:
  US08/484,730
• Time in Patent Office: 2,232 Days
• Field of Search: 395/800, 395/376, 712/1, 712/200, 712/209, 348/384, 348/403, 348/404, 348/405, 348/441, 341/50, 382/303
• US Class Current: 712/209
• CPC Class Codes: G06F 12/0207 with multidimensional access, e.g. row/column, matrix
• CPC Class Codes: G06F 12/04 Addressing variable-length words or parts of words
• CPC Class Codes: G06F 12/0607 Interleaved addressing
• CPC Class Codes: G06F 13/16 for access to memory bus G06F13/28 takes precedence
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence
• CPC Class Codes: G06F 9/3867 using instruction pipelines
• CPC Class Codes: G06F 9/4494 data driven
• CPC Class Codes: H04N 19/13 Adaptive entropy coding, e.g. adaptive variable length coding [AVLC] or context adaptive binary arithmetic coding [CABAC]
• CPC Class Codes: H04N 19/42 characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation H04N19/635 takes precedence
• CPC Class Codes: H04N 19/423 characterised by memory arrangements H04N19/433 takes precedence
• CPC Class Codes: H04N 19/44 Decoders specially adapted therefor, e.g. video decoders which are asymmetric with respect to the encoder
• CPC Class Codes: H04N 19/61 in combination with predictive coding
• CPC Class Codes: H04N 19/91 Entropy coding, e.g. variable length coding [VLC] or arithmetic coding

Abstract

A plurality of processing stages interposed between an input and an output of a system including a pipeline machine interconnect for conveyance of tokens along the pipeline. Control and or data tokens in the form of universal adaptation units interface with all of the stages in the pipeline and alternatively interact with selected stages in the pipeline so that the processing stages in the pipeline are afforded enhanced flexibility in configuration and processing. In one embodiment of the system, the stages accept a data stream having portions encoded according to respectively different video formats. At least one of the stages includes circuitry for generating signals to indicate an end-of-picture data decoding. The stage includes state machine logic that is responsive to the generated signals for effecting an end of picture data decoding by clearing the pipeline. A method of clearing the pipeline includes receiving a data stream, indicating an end of picture data decoding, and clearing the pipeline when an end of picture data decoding has been indicated.

Claims

1. A system having an input and an output, comprising:

a plurality of processing stages forming a pipeline between the input and the output;

an interface interconnecting the plurality of processing stages for conveyance of tokens along the pipeline; and

control and or data tokens in the form of universal adaptation units for interfacing with all of the stages in the pipeline and interacting with selected stages in the pipeline, each of said control and data tokens including a plurality of data words and each of said data words having an extension bit which indicates a presence of additional data words therein, a state of said extension bit indicating a first word of said data words, said processing stages in said pipeline thereby enabled with flexibility in configuration and processing.

2. The system of claim 1 wherein one of said processing stages includes an inverse quantizer recognizing a first QUANT_TABLE token of said conveyed tokens.

3. The system of claim 2 wherein said inverse quantizer generates a second QUANT_TABLE token having a plurality of quantization table values, said second QUANT_TABLE token being generated in response to a first state of said extension bit of said first word of said first QUANT_TABLE token.

4. The system of claim 3 wherein said second QUANT_TABLE token is conveyed to a subsequent processing stage of said pipeline.

5. The system of claim 2 wherein responsive to a second state of said extension bit of said first word of said first QUANT_TABLE token, said inverse quantizer installs a quantization table of said first QUANT_TABLE token in a memory.

6. The system of claim 2 wherein said inverse quantizer is connected with at least one other of said processing stages by a sender, a receiver, and a clock connected to said sender and said receiver.

7. The system of claim 6 wherein said clock includes transitions from a first state to a second state so that data is transferred from said sender to said receiver upon a respective clock transition only when said sender is ready and said receiver is ready.

8. The system of any one of claims 1, 2, 3, 4, 5, 6, or 7 further including electrical validation circuitry in a respective processing stage to generate a validation signal for a first state when data stored in said respective stage is valid and for a second state when data stored in said respective stage is invalid, said state defining said respective stage'"'"'s ability to accept data ready.

9. The system of claim 8 wherein said validation circuitry includes at least one validation storage device to store said validation signal for a corresponding pipeline stage.

10. The system of claim 9 further including an acceptance signal connecting an adjacent pair of processing stages and conveying an acceptance signal indicative of the ability of a successive pipeline stage to load data stored in a preceding pipeline stage.

11. The system of claim 10 further including enabling circuitry connected to said at least one validation data storage device for generating an enabling signal to enable loading of data and validation signals into additional validation data storage devices.

12. The system of claim 11 wherein said at least one validation data storage device includes a primary data storage device and a secondary data storage device.

13. The system of claim 12 wherein said data and said validation signal is loaded into a respective primary storage device at the same time.

14. The system of claim 12 wherein data is loaded into a respective primary data storage device when said acceptance signal assumes an enabling state, said acceptance signal assuming said enabling state only when the acceptance signal associated with a data storage device of a next successive pipeline stage is in said enabling state or the data in the data storage device of said next successive pipeline stage is invalid.

15. The system as recited in claim 14 wherein the flexibility of said tokens facilitates system expansion and or alteration.

16. The system of claim 1 wherein each of said processing stages includes both primary and secondary storage.

17. The system of claim 1 wherein said stages in said pipeline are reconfigurable in response to recognition of selected tokens.

18. The system of claim 17 wherein said tokens are dynamically adaptive.

19. The system as recited in any of claims 16-18 wherein said tokens are position dependent upon said processing stages for performance of functions.

20. The system as recited in any of claims 16-18 wherein said tokens are position independent of said processing stages for performance of functions.

21. The system as recited in any of claims 16-18 wherein said tokens are altered by interfacing with said stages.

22. The system as recited in any of claims 16-18 wherein said tokens interact with all of said stages.

23. The system as recited in any of claims 16-18 wherein said tokens interact with some but less than all of said processing stages.

24. The system as recited in any of claims 16-18 wherein said tokens interact with only predetermined ones of said processing stages.

25. The system as recited in any of claims 16-18 wherein said tokens interact with adjacent processing stages.

26. The system as recited in any of claims 16-18 wherein said tokens interact with non-adjacent processing stages.

27. The system as recited in any of claims 16-18 wherein said tokens reconfigure said processing stages.

28. The system as recited in any of claims 16-18 wherein said tokens are position dependent for some functions and position independent for other functions in said pipeline.

29. The system as recited in any of claims 16-18 wherein said tokens provide a basic building block for the pipeline system.

30. The system as recited in any of claims 16-18 wherein the interaction of said tokens with a processing stage in said pipeline is conditioned by the previous processing history of said processing stage.

31. The system as recited in any of claims 16-18 wherein each of said tokens has an address field which characterizes a respective token.

32. The system as recited in claim 31 wherein interactions with a processing stage are determined by at least one of said address fields.

33. The system as recited in claim 31 wherein at least some of said address fields are of variable length.

34. The system as recited in claim 31 wherein at least some of said address fields are Huffman coded.

35. The system as recited in any of claims 16-18 wherein said tokens include an extension bit for each token.

36. The system as recited in claim 35 wherein said extension bit indicates the presence of additional words in a respective token.

37. The system as recited in claim 36 wherein said extension bit identifies the last word in said token.

38. The system as recited in any of claims 16-18 wherein said tokens are generated by a processing stage.

39. The system as recited in any of claims 16-18 wherein said tokens include data for transfer to said stages in said pipeline.

40. The system as recited in any of claims 16-18 wherein said tokens are devoid of data.

41. The system as recited in any of claims 16-18 wherein some of said tokens are identified as DATA tokens and provide data to said processing stages in said pipeline.

42. The system as recited in any of claims 16-18 wherein some of said tokens are identified as control tokens and only condition said processing stages in said pipeline.

43. The system as recited in claim 42 wherein said conditioning includes reconfiguring of said processing stages in said pipeline.

44. The system as recited in any of claims 16-18 wherein said tokens provide both data and conditioning to said processing stages in said pipeline.

45. The system as recited in any of claims 16-18 wherein said tokens identify coding standards to said processing stages in said pipeline.

46. The system as recite claims 16-18 wherein at least some of said tokens operate independently of any coding standard among said processing stages in said pipeline.

47. The system as recited in any of claims 16-18 wherein said tokens are capable of successive alteration by said processing stages in said pipeline.

48. The system as recited in any of claims 16-18 wherein the interactive flexibility of said tokens in cooperation with said processing stages facilitates greater functional diversity of said processing stages for resident structure in said pipeline.

49. The system as recited in any of claims 16-18 wherein said tokens are capable of facilitating a plurality of functions within any processing stage in said pipeline.

50. The system as recited in any of claims 16-18 wherein said tokens are hardware based.

51. The system as recited in any of claims 16-18 wherein said tokens are software based.

52. The system as recited in any of claims 16-18 wherein said tokens facilitate more efficient uses of system bandwidth.

53. The system as recited in any of claims 16-18 wherein at least some of said tokens provide data and control simultaneously to said processing stages in said pipeline.

54. The system of claim 1, wherein:

the interface couples the stages of the pipeline according to a valid/accept protocol.

55. The system of claim 1, wherein:

the interface is a two-signal interface.