Optical reader with condensed CMOS circuitry

• US 6,276,605 B1
• Filed: 10/29/1998
• Issued: 08/21/2001
• Est. Priority Date: 08/25/1995
• Status: Expired due to Term

• Current Assignee: PTO (Safe Fleet Holdings LLC)
• Original Assignee: PTO (Safe Fleet Holdings LLC)
• Inventors: Olmstead, Bryan L., Colley, James E.
• Primary Examiner(s): TREMBLAY, MARK STEPHEN
• Application Number:
  US09/183,230
• Time in Patent Office: 1,027 Days
• Field of Search: 235/455, 235/462.01, 235/439, 235/440, 235/460, 235/462.41, 235/470, 235/454
• US Class Current: 235/462.41
• CPC Class Codes: G06K 7/10752 Exposure time control
• CPC Class Codes: G06K 7/1093 sensing, after transfer of the image of the data-field to an intermediate store, e.g. storage with cathode ray tube
• CPC Class Codes: H04N 25/40 Extracting pixel data from image sensors by controlling scanning circuits, e.g. by modifying the number of pixels sampled or to be sampled
• CPC Class Codes: H04N 25/533 by using differing integration times for different sensor regions
• CPC Class Codes: H04N 25/77 Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
• CPC Class Codes: H04N 3/155 Control of the image-sensor operation, e.g. image processing within the image-sensor

Abstract

An optical or symbol reader including CMOS circuitry preferably integrated on a single chip. A CMOS optical reader chip comprises a CMOS imaging array having a plurality of pixels each with a dedicated pixel-site circuit. Charge is accumulated at each pixel location transferred upon demand to a common bus. In a preferred embodiment, exposure time of the imaging array is controlled using a feedback loop. One or more exposure control pixels are positioned adjacent to or within the imaging array and receive light along with the imaging array. The charge of the exposure control pixel or pixels is measured against a threshold level, and the amount of time taken to reach the threshold level determines the time exposure of the pixels of the imaging array. CMOS signal processing circuitry is employed which, in combination with the exposure control circuitry, minimizes time-to-read over a large range of light levels, while performing spatially optimal filtering. Clocking cycles and control signals are time-adjusted in accordance with the varying output frequency of the imaging array so as to provide invariant frequency response by the signal processing circuitry. A multi-dimensional CMOS imaging array is also provided having simultaneous pixel exposure with non-destructive readout of the pixel contents.

Claims

1. Apparatus for reading encoded symbols, comprising:

an integrated chip fabricated using a CMOS process, said integrated chip comprising

an imaging array including a plurality of photosensitive cells;

a clock generator connected to said imaging array;

a common output bus connected to said imaging array;

an address generator connected to said imaging array, whereby said photosensitive cells are accessed according to a pattern;

an amplifier connected to said common output bus, said amplifier outputting an imaging signal comprising a sequence of pixel output values corresponding to an amount of light collected at each photosensitive cell of the imaging array; and

an edge detector connected to said amplifier, said edge detector comprising circuitry for detecting transitions between relatively higher and relatively lower amplitudes in said imaging signal corresponding to darker and lighter portions of a symbol being read; and

a symbology decoder coupled to said edge detector.

2. The apparatus of claim 1, further comprising an exposure time controller connected to said clock generator, whereby an exposure time of said imaging array is adjusted.

3. The apparatus of claim 2, wherein said exposure time controller is integrated within said integrated chip.

4. The apparatus of claim 1, wherein said symbology decoder is integrated within said integrated chip.

5. The apparatus of claim 1, wherein said imaging array is two-dimensional.

6. The apparatus of claim 1, wherein said photosensitive cells are randomly accessible through unique addresses generated by said address generator, said addresses being serially generated in response to a clocking signal.

7. The apparatus of claim 1, further comprising an analog-to-digital (A/D) converter interposed between said amplifier and said symbology decoder, said A/D converter outputting a digitized imaging signal.

8. The apparatus of claim 1, wherein said photosensitive cells are arranged in a two-dimensional pattern only partially filling an area defined by an outer perimeter of said imaging array.

9. The apparatus of claim 8, further comprising at least one pixel-site circuit controlling exposure time of said individually addressable photosensitive cells, said at least one pixel-site circuit being integrated with said imaging array and physically located within said outer perimeter of said imaging array in empty space not occupied by photosensitive cells.

10. A method for manufacturing an image reader, comprising the steps of:

integrating, on a single integrated chip, an imaging array including a plurality of photosensitive cells, a clock generator, a common output bus, an address generator, an amplifier, and an edge detector, whereby said photosensitive cells are individually accessible in response to address generated by said address generator, and whereby said imaging array outputs an electrical signal to said common output bus for amplification by said amplifier;

connecting an output of said amplifier to an analog-to-digital (A/D) converter, said A/D converter outputting a digitized signal;

connecting said digitized signal to said edge detector; and

connecting said edge detector to a symbology decoder.

12. The method of claim 10, further comprising the step of integrating an exposure control circuit on said integrated chip, said exposure control circuit controlling an exposure period of said photosensitive cells.

13. The method of claim 10, further comprising the step of integrating said symbology decoder on said integrated chip.

11. The method of claimed 10, further comprising the step of fabricating said integrated chip using a CMOS process.

14. A single-chip bar code reader, comprising:

an imaging array located on an integrated chip, said imaging array comprising a plurality of photosensitive cells;

a clock generator located on said integrated chip and connected to said imaging array;

a common output bus located on said integrated chip and connected to said imaging array;

an address generator located on said integrated chip and connected to said imaging array, said address generator outputting address signals whereby said photosensitive cells can be individually accessed;

an amplifier located on said integrated chip and connected to said output bus, said amplifier outputting a signal comprising a series of substantially discrete amplitudes corresponding to levels of accumulated charge at said plurality of photosensitive cells;

an analog-to-digital (A/D) converter located on said integrated chip and connected to said signal, said A/D converter outputting a digitized signal;

an edge detector located on said integrated chip and coupled to said digitized signal; and

a symbology decoder coupled to said edge detector.

15. The single-chip bar code reader of claim 14, further comprising an exposure control circuit connected to said clock generator, whereby an exposure period of said photosensitive cells is altered in response to an amount of detected light.

16. The single-chip bar code reader of claim 14, wherein said integrated chip is fabricated using a CMOS process.

17. The single-chip bar code reader of claim 14, wherein said symbology decoder is located on said integrated chip.

18. Apparatus for reading encoded symbols, comprising:

an integrated chip fabricated using a CMOS process, said integrated chip comprising

an imaging array including a plurality of photosensitive cells;

a clock generator connected to said imaging array;

a common output bus connected to said imaging array;

p2 an address generator connected to said imaging array, whereby said photosensitive cells are accessed according to a pattern;

an amplifier connected to said common output bus, said amplifier outputting an imaging signal comprising a sequence of pixel output values corresponding to an amount of light collected at each photosensitive cell of the imaging array; and

a symbology decoder coupled to said amplifier.

19. A method for manufacturing an image reader, comprising the steps of:

integrating, on a single integrated chip, an imaging array including a plurality of photosensitive cells, a clock generator, a common output bus, an address generator, an amplifier, and a symbology decoder, whereby said photosensitive cells are individually accessible in response to addresses generated by said address generator, and whereby said imaging array outputs an electrical signal to said common output bus for amplification by said amplifier;

connecting an output of said amplifier to an analog-to-digital (A/D) converter, said A/D converter outputting a digitized signal; and

connecting said digitized signal to said symbology decoder.

20. A single-chip bar code reader, comprising:

an imaging array located on an integrated chip, said imaging array comprising a plurality of photosensitive cells;

a clock generator located on said integrated chip and connected to said imaging array;

a common output bus located on said integrated chip and connected to said imaging array;

an address generator located on said integrated chip and connected to said imaging array, said address generator outputting address signals whereby said photosensitive cells can be individually accessed;

an amplifier located on said integrated chip and connected to said output bus, said amplifier outputting a signal comprising a series of substantially discrete amplitudes corresponding to levels of accumulated charge at said plurality of photosensitive cells;

an analog-to-digital (A/D) converter connected said signal, said A/D converter outputting a digitized signal; and

a symbology decoder located on said integrated chip, said symbology decoder connected to said digitized signal.