Master isochronous clock structure having a clock controller coupling to a CPU and two data buses

• US 6,279,058 B1
• Filed: 07/02/1998
• Issued: 08/21/2001
• Est. Priority Date: 07/02/1998
• Status: Expired due to Term

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Gulick, Dale E.
• Primary Examiner(s): Lee, Thomas
• Assistant Examiner(s): Cao, Chun
• Application Number:
  US09/109,440
• Time in Patent Office: 1,146 Days
• Field of Search: 713/400, 713/501, 713/600, 713/500, 713/401, 711/167, 370/512, 710/5, 710/58.61
• US Class Current: 710/58
• CPC Class Codes: G06F 1/12 Synchronisation of different clock signals provided by a plurality of clock generators
• CPC Class Codes: G06F 13/4217 with synchronous protocol

Abstract

A frame-rate clock of a plurality of data buses is synchronized to a master clock signal. The master clock signal may be derived from the existing clock signals within the computer system or from data received from an external source. The master clock signal may also be used by an operating system scheduler to schedule tasks that generate or consume blocks of isochronous data. The drift of a device clock signal relative to a master clock signal is measured and used to synchronize the device clock signal. For example, a mechanism may monitor the level of data in a data buffer. The level of data in the data buffer is a measure of the drift between the clock generating the data and the clock consuming the data. Based upon the level of data in the buffer, synchronization information is provided to synchronize the rates of the clock signals that generate and consume the data.

Claims

1. A computer system comprising:

a central processing unit (CPU);

a first data bus coupled to said CPU and configured to transfer data at a first clock rate;

a second data bus coupled to said CPU and configured to transfer data at a second clock rate;

a clock controller coupled to said CPU, said first data bus and said second data bus, and configured to receive a clock signal from said first data bus and output a master clock signal to said second data bus, such that said second clock rate approximates said first clock rate.

2. The computer system of claim 1 wherein said first clock rate and said second clock rate are frame clock rates.

3. The computer system of claim 2 wherein said second clock rate approximates a multiple of said first clock rate.

4. The computer system of claim 2 wherein said second clock rate approximates a divisor of said first clock rate.

5. The computer system of claim 2 wherein said master clock signal is provided to an interrupt controller of said CPU and software operating on said CPU schedules tasks based on an output of said interrupt controller.

6. The computer system of claim 2 wherein said second clock rate is synchronized with said first clock rate.

7. The computer system of claim 2 further comprising a third data bus coupled to said CPU, and configured to transfer data at a third clock rate and to receive said master clock signal such that said third clock rate approximates said first clock rate.

8. The computer system of claim 2 further comprising a third data bus and a signal processor coupled between said third data bus and said CPU, and configured to transfer data at a third clock rate, wherein said signal processor is configured to interpolate said data to match said first clock rate.

18. The computer system of claim 1, wherein one of the data buses is configured to receive the isochronous data from an isochronous device.

19. The computer system of claim 18, wherein one of the data buses comprises a Universal Serial Bus (USB).

20. The computer system of claim 18, wherein one of the data buses comprises an Institute of Electrical and Electronics Engineers (IEEE) 1394 bus.

21. The computer system of claim 18, wherein one of the data buses comprises an Audio Codec '"'"'97 (AC '"'"'97) bus.

9. A computer system comprising:

a central processing unit (CPU);

a first data bus coupled to said CPU and configured to receive data from a first isochronous device at a first clock rate;

a second data bus coupled to said CPU and configured to transfer data at a second clock rate;

a clock controller coupled to said CPU, said first data bus and said second data bus, and configured to receive said data from said isochronous device and output a master clock signal based on a rate of said data to said second data bus, such that said second clock rate approximates said first clock rate.

10. The computer system of claim 9 wherein said first clock rate and said second clock rate are frame clock rates.

11. The computer system of claim 10 wherein said second clock rate approximates a multiple of said first clock rate.

12. The computer system of claim 10 wherein said second clock rate approximates a divisor of said first clock rate.

13. The computer system of claim 10 wherein said master clock signal is provided to an interrupt controller of said CPU and an operating system operating on said CPU schedules tasks based on an output of said interrupt controller.

14. The computer system of claim 10 wherein said second clock rate is synchronized with said first clock rate.

15. The computer system of claim 10 further comprising a third data bus coupled to said CPU and configured to transfer data at a third clock rate and to receive said master clock signal such that said third clock rate approximates said first clock rate.

16. The computer system of claim 10 further comprising a third data bus and a signal processor coupled between said third data bus and said CPU, and configured to transfer data at a third clock rate, wherein said signal processor is configured to interpolate said data to match said first clock rate.

17. The computer system of claim 10 further comprising a third data bus configured to receive data from a second isochronous device at a third clock rate and a signal processor coupled between said third data bus and said CPU, wherein said signal processor is configured to interpolate said data to match said first clock rate.

22. A computer system comprising:

a central processing unit (CPU);

a first data bus coupled to the CPU and configured to transfer isochronous data at a first clock rate;

a second data bus coupled to the CPU and configured to transfer the isochronous data at a second clock rate;

an internal clock configured to output a clock signal; and

a clock controller coupled to the CPU, the first data bus, the second data bus, and the internal clock and configured to synchronize the first clock rate and the second clock rate to the clock signal so that transfers of the isochronous data are synchronized to the clock signal.

23. The computer system of claim 22, wherein the clock controller is implemented in software.

24. The computer system of claim 22, wherein the internal clock comprises a system clock configured to clock the CPU.

25. The computer system of claim 22, wherein the internal clock comprises an IEEE 1394 bus clock.

26. The computer system of claim 22, wherein the first and second clock rates are frame clock rates.

27. The computer system of claim 22, wherein the clock controller is configured to synchronize the first clock rate and the second clock rate by interpolation.

28. The computer system of claim 22, further comprising an isochronous device coupled to the first or second data bus and configured to generate or consume isochronous data, wherein the clock controller is further configured to synchronize a rate at which the isochronous device generates or consumes isochronous data to the clock signal.

29. The computer system of claim 28, wherein the clock controller is configured to synchronize the rate at which the isochronous device generates or consumes isochronous data to the clock signal by adjusting a frame rate of the isochronous device.