Apparatus and method for verifying a multi-component electronic design

• US 6,279,146 B1
• Filed: 06/18/1999
• Issued: 08/21/2001
• Est. Priority Date: 01/06/1999
• Status: Expired due to Fees

• Current Assignee: Ravesim, Inc.
• Original Assignee: SimuTech Corp.
• Inventors: Evans, Ed, Jurasek, Dave
• Primary Examiner(s): Smith, Matthew
• Assistant Examiner(s): Kik, Phallaka
• Application Number:
  US09/336,485
• Time in Patent Office: 795 Days
• Field of Search: 716/46, 716/16, 716/18, 703/14, 703/20-21, 703/25
• US Class Current: 716/113
• CPC Class Codes: G06F 30/33 Design verification, e.g. functional simulation or model checking
• CPC Class Codes: G06F 30/331 with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation

Abstract

A verification engine for verifying the design of a target system having a plurality of components interconnected by a plurality of target system buses is disclosed. The verification engine comprises a first hardware model and a second hardware model, both configured as a component and having a set of hardware model input/output pins. In addition, a first bus wrapper is connected to the first hardware model and a second bus wrapper is connected to the second hardware model. Further, a set of bus lines are each connected to the first bus wrapper and the second bus wrapper. Each bus wrapper also has switchable communicative circuitry that switchably communicatively connects each hardware model input/output pin to a bus line and has a control block controlling the switchable communicative circuitry. A system controller is connected to at least some of the bus lines and is adapted to transmit a sequence of time synchronization information to each bus wrapper control block by way of the bus lines. Finally, responsive to a predetermined one of the time slot numbers both of the control blocks switch at least one input/output pin into communicative contact with a the bus line so that at least one input/output line from the first hardware model is connected to an input/output line of the second hardware model.

Claims

1. A verification engine for verifying the design of a target system having a plurality of components interconnected by a plurality of target system buses, and verification engine comprising:

a. a first hardware model and a second hardware model, each configured as a said component and having a set of hardware model input/output pins;

b. a first bus wrapper connected to said first hardware model and a second bus wrapper connected to said second hardware model;

c. a set of bus lines, each said bus line being connected to said first bus wrapper and said second bus wrapper;

d. wherein each said bus wrapper further has switchable communicative circuitry that switchably communicatively connects each said hardware model input/output pin to a bus line and has a control block controlling said switchable communicative circuitry;

e. a system controller connected to at least some of said bus lines and adapted to transmit a sequence of time synchronization information to each said bus wrapper control block, said time synchronization information sufficient to permit said control blocks to uniformly determine a time slot number; and

f. wherein said control blocks uniformly determine said time slot number in response to said time synchronization information and in response thereto each control block switches at least one said input/output pin into communicative contact with a said bus line so that at least one said input/output pin from said first hardware model is connected to at least one said input/output pin of said second hardware model.

2. The verification engine of claim 1 including additional hardware models each connected to an additional bus wrapper which is connected to said set of bus lines.

3. The verification engine of claim 1 wherein said system controller transmits one out of a set of target system clock information during each time slot number and said first hardware model has a first target system clock input pin and said first bus wrapper is capable of generating a clock input and sending it to said first target system clock input pin in response to a first target system clock indicating signal.

4. The verification engine of claim 3 wherein said set of target system clock information includes a null command which indicates that no target system clock signal should be sent by any of said bus wrappers.

5. The verification engine of claim 3 wherein said second hardware model includes a second target system clock input pin and said second bus wrapper further includes a second bus wrapper target system clock output pin connected to said second target system clock input pin and wherein said second bus wrapper determines, on each said time slot, based on said target system clock indicating signal whether to send a target system clock signal over said second bus wrapper target system clock output pin.

6. The verification engine of claim 5 wherein said set of target system clock information includes a first clock indicating signal and a second clock indicating signal and wherein said first bus wrapper sends a target system clock over said first bus wrapper target system clock output pin in response to said first clock indicating signal and said second bus wrapper sends a target system clock over said second bus wrapper target system clock output pin in response to said second clock indicating signal.

7. The verification engine of claim 3 wherein said set of target system clock information further includes a second clock indicating signal and said first hardware model further includes a second target system clock input pin and said first bus wrapper is further capable of generating a second clock input and sending it to said second target system clock input pin in response to a second target system clock indicating signal.

8. The verification engine of claim 1 in which said time synchronization information includes a time slot number that is transmitted in a plurality of time slots.

9. A verification engine for verifying the design of a target system having a plurality of components interconnected by a plurality of target system buses, said verification engine comprising:

a. a plurality of reconfigurable bus wrappers, each having a bus wrapper/hardware model set of pins and a bus wrapper/bus line set of pins, switchable communicative circuitry that switchably communicatively connects each said bus wrapper/hardware model set of pins to a bus wrapper/bus line pin and a control block controlling said switchable communicative circuitry;

b. a set of bus lines, each said bus line having a bus line/bus wrapper pin for each bus wrapper, each said bus line/bus wrapper pin being connected to a bus wrapper/bus line pin;

c. a system controller connected to at least some of said bus lines and adapted to transmit time synchronization information sufficient for said control block to uniformly determine a corresponding time slot number; and

d. wherein, responsive to said time synchronization information, each said control block determines said corresponding time slot number and responsive to said determined time slot number, switches at least one bus wrapper/hardware model pin into communicative contact with a said bus wrapper/bus line pin.

10. The verification engine of claim 9 wherein said time synchronization information includes a time slot number.

11. A method of determining drive direction between a first circuit node that is communicatively connected to a first driver input pin of a first driver and a second circuit node that is communicatively connected to a second driver input pin of a second driver, said first driver and said second driver being connected by a connecting line, and wherein said first and second circuit nodes are tentatively commanded to be connected by enabling either said first driver or said second driver with input from said first circuit node or said second circuit node respectively, said method comprising:

(a) automatically forming a first test result by determining if said first circuit node is being driven; and

(b) recording said first test result in a first format.

12. The method of determining drive direction of claim 11, further including the steps of:

(a) automatically forming a second test result by determining if said second circuit node is being driven;

(b) recording said second test result in said first format;

(c) comparing said first test result to said second test result;

(d) if said first test result is different from said second test result, using said first driver or said second driver to drive said connecting line from whichever of said circuit nodes is being driven.

13. The method of claim 12 wherein if both said first circuit node and said second circuit node are being driven, this is recorded as a fight condition and if neither one of said first circuit node and said second circuit node is being driven this is recorded as a float condition.

14. The method of claim 13 wherein said fight condition causes a cancellation of said tentatively commanded connection of said first and second nodes.

15. The method of claim 13 wherein said float condition causes an interrupt to system operation.

16. The method of claim 12 wherein said first node encompasses a first conductive link between a first hardware model and a first bus wrapper and said second node encompasses a second conductive link between a second hardware model and a second bus wrapper and said connecting line is a bus line connecting said first bus wrapper to said second bus wrapper.

17. The method of claim 12 wherein said first node is one out of a multiplicity of first nodes, each encompassing a conductive link between a first hardware model and a first bus wrapper that is part of a verification engine and wherein said second node is one of a multiplicity of second nodes, each encompassing a conductive link between a second hardware model and a second bus wrapper included in a verification engine, and a bus line is one out of a multiplicity of bus lines connecting said first bus wrapper to said second bus wrapper.

18. The method of claim 17 wherein said verification engine further includes a bus fight reporting table that specifies for each bus line at least one binary value indicating whether a prospective bus fight on said bus line is to result in an interruption of verification engine operation.

19. The method of claim 18 wherein said bus lines are time multiplexed into time slots and in which said bus fight reporting table specifies for each bus line a binary value for each time slot indicating whether a prospective bus fight on said bus line in said time slot is to result in an interruption of verification engine operation.

20. The method of claim 17 wherein said verification engine further includes a bus float reporting table that specifies for each bus line at least one binary value indicating whether a prospective bus float on said bus line is to result in an interruption of verification engine operation.

21. The method of claim 20 wherein operation of said bus lines is time multiplexed into time slots and wherein said bus float reporting table specifies for each bus line, for each time slot, a binary value indicating whether a prospective bus float on said bus line in said time slot will result in an interruption of verification engine operation.

22. A bus adapted to selectively couple a first electrical component having a set of first component input/output pins to a second electrical component having a set of second component input/output pins, comprising:

(a) a first bus wrapper having;

(i) a set of first bus wrapper-to-component pins adapted to be connected to said first component input/output pins;

(ii) a set of first bus wrapper bus line pins;

(iii) a set of latches, each said latch being switchably communicatively connected to a said first bus wrapper-to-component pin and to a said first bus wrapper bus line pin; and

(iv) a local condition sensor;

(b) a second bus wrapper having;

(i) a set of second bus wrapper-to-component pins adapted to be connected to said second component input/output pins;

(ii) a set of second bus wrapper bus line pins; and

(iii) a set of latches, each said latch being switchably communicatively connected to a said second bus wrapper-to-component pin and to a said second bus wrapper bus line pin;

(c) a set of bus line conductors connecting each said first bus wrapper bus line pin to a said second bus wrapper bus line pin; and

(d) a system controller having a set of system controller bus line pins connected to said set of bus line conductors and adapted to transmit to said bus wrappers time synchronization information sufficient for said bus wrappers to uniformly determine a time slot number; and

(e) wherein each bus wrapper is adapted to determine, for each said time slot number which, if any, of its said latches is active during said time slot and in which said first bus wrapper is further adapted to determine, at least in part by said local condition sensor and said time slot number, which said active latches will be switched into a transmitting communicative coupling with a said first bus wrapper-to-component pin and which will be switched into a transmitting communicative coupling with a said first bus wrapper bus line pin.

23. The bus of claim 22 wherein said local condition sensor senses whether a first input/output pin of said first electrical component is driving.

24. A method for verification testing of a target system design made up of a plurality of components connected by a plurality of buses that permit a defined flow of data between said components, said method comprising:

(a) connecting hardware models of at least some of said components with a time multiplexed bus; and

(b) controlling said time multiplexed bus to permit said defined flow of data between said hardware models.

25. An apparatus for interfacing to an integrated circuit that contains bi-directional pins, said apparatus comprising:

a. a soft drive adapted to soft drive a said bi-directional pin high during a high drive time and to soft drive said bi-directional pin low during a low drive time;

b. a first flip-flop configured to save the output of said bi-directional pin during its high drive time;

c. a second flip-flop configured to save the output of said bi-directional pin during its low drive time; and

d. an EXclusive OR gate having a first input that is connected to an output of said first flip-flop and a second input that is connected to an output of said second flip-flop and having an output which, after said high and low drive times, is thereby indicative of pin drive direction.

26. The apparatus of claim 25, further including a bi-directional buffer for said bi-directional pin and wherein said bi-directional buffer changes drive direction in response to said output of said EXclusive OR gate.