Method and apparatus for reducing parasitic bipolar current in a silicon-on-insulator transistor

• US 6,281,737 B1
• Filed: 11/20/1998
• Issued: 08/28/2001
• Est. Priority Date: 11/20/1998
• Status: Expired due to Term

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Kuang, Jente Benedict, Lu, Pong-Fei, Saccamango, Mary Joseph
• Primary Examiner(s): Cunningham, Terry D.
• Assistant Examiner(s): TRA, ANH QUAN
• Application Number:
  US09/196,907
• Time in Patent Office: 1,012 Days
• Field of Search: 327/382, 327/534, 327/535
• US Class Current: 327/382
• CPC Class Codes: H03K 17/162 without feedback from the output circuit to the control circuit
• CPC Class Codes: H03K 19/0027 in field effect transistor circuits
• CPC Class Codes: H03K 19/00361 in field effect transistor circuits
• CPC Class Codes: H03K 2217/0018 Special modifications or use of the back gate voltage of a FET

Abstract

In a method and apparatus for reducing parasitic bipolar current in an insulated body, field effect transistor (“FET”), for an n-type FET, the body of the insulated body NFET is electrically isolated, responsive to turning on the NFET. This permits a charge to accumulate on the body in connection with turning the NFET on, temporarily lowering the threshold voltage for the insulated body NFET. Responsive to turning off the insulated body NFET, at least a portion of the charge on the body is discharged. This discharging of the body reduces parasitic bipolar current which would otherwise occur upon turning the NFET back on if the body had charged up during the time when the NFET was off. For a p-type FET that is susceptible to parasitic bipolar current, the body is discharged responsive to turning off the PFET, and isolated responsive to turning on the PFET.

Claims

1. An apparatus for reducing parasitic bipolar current in a field effect transistor (“

FET”

), comprising;

a first FET, having a body disposed, at least in part, on an insulator; and

control circuitry coupled to the body and a gate electrode of the first FET, for controlling charge on the body responsive solely to a single control circuitry input voltage, the voltage also being applied directly to the gate electrode, wherein the first FET is operable to turn on and off responsive to the voltage applied to the gate electrode, and wherein the control circuitry has a discharge path and the control circuitry is operable to turn on the path and discharge at least a portion of any charge on the body when the first FET is turned off, and to turn off the path and allow the body to float and charge to accumulate on the body when the first FET is turned on.

2. The apparatus of claim 1, wherein the discharge path comprises a body-charge control FET, having first and second conducting electrodes and a gate electrode, wherein the body-charge control FET first conducting electrode is electrically coupled to the body of the first FET and the body-charge control FET second conducting electrode is electrically coupled to an electrical sink, and wherein the control circuitry comprises an inverter having an inverter input electrically coupled to the first FET gate electrode, and an inverter output electrically coupled to the body-charge control FET gate electrode, so that the voltage applied to the first FET gate electrode being above a certain first voltage level tends to drive the inverter output voltage low, turn off the body-charge control FET and electrically isolate the body from the sink, thereby permitting the body to float and a charge to accumulate on the body, and the voltage applied to the first FET gate electrode being below a certain second voltage level tends to drive the inverter output voltage high, turn on the body-charge control FET and electrically couple the body to the sink, thereby discharging at least a portion of any charge accumulated on the body.

3. The apparatus of claim 2, wherein the first FET first and second conducting electrodes couple first circuitry to second circuitry, respectively, and the control circuitry is operable independently of the first and second circuitry since the control circuitry controls charge on the body of the first FET solely responsive to the voltage applied to the gate electrode of the first FET.

4. The apparatus of claim 3, wherein the first FET is a logic device in one leg of a logic circuit.

5. The apparatus of claim 3, wherein the first FET is a logic device in one branch of a multiplexer circuit.

6. The apparatus of claim 2, wherein the first FET is an NFET, the apparatus comprising:

a second FET having a body disposed, at least in part, on an insulator, wherein the second FET is a PFET; and

second control circuitry coupled to the body of the second FET and the gate of the first FET, for controlling charge on the second FET body responsive to a voltage applied to the gate electrode of the second insulated body FET.

7. The apparatus of claim 6, wherein the second control circuitry comprises a second body-charge control FET, the second body-charge control FET being a PFET having first and second conducting electrodes and a gate electrode, wherein the second body-charge control FET first conducting electrode is electrically coupled to the body of the second FET, the second body-charge control FET second conducting electrode is electrically coupled to an electrical source, and the second body-charge control FET gate electrode is coupled to the gate electrode of the first FET, so that the voltage applied to the second FET gate electrode being above a certain first voltage level tends to turn on the second body-charge control FET and electrically couple the second FET to the electrical source, thereby tending to discharge the body, and the voltage applied to the second FET gate electrode being below a certain second voltage tends to turn off the second body-charge control FET and electrically isolate the second FET body from the source, thereby permitting the body to float and a charge to accumulate on the body.

8. A method for reducing parasitic bipolar current in an n-type, field effect transistor (“

NFET”

) having a body disposed, at least in part, on an insulator, comprising the steps of;

a) turning off a control circuitry discharge path for the NFET responsive solely to a single voltage applied directly to a gate electrode of the NFET, wherein turning on the NFET by the single voltage turns off the discharge path and permits the body to float and a charge to accumulate on the body; and

b) turning on the discharge path responsive solely to the single voltage applied directly to the NFET gate electrode, wherein turning off the NFET by the single voltage turns on the discharge path and discharges at least a portion of any charge on the body of the NFET.

9. The method of claim 8, wherein step b) comprises electrically coupling the NFET body to a sink, the sink having a voltage lower than a voltage level of the accumulated charge, wherein the NFET body is thus coupled to the sink whenever the NFET gate electrode voltage is turned off.

10. A method for reducing parasitic bipolar current in an p-type, field effect transistor (“

PFET”

) having a body disposed, at least in part, on an insulator, comprising the steps of;

a) turning on a control circuitry discharge path responsive solely to a single voltage applied directly to a gate electrode of the PFET, wherein turning off the PFET by the single voltage turns on the discharge path and discharges at least a portion of any charge on the body of the PFET; and

b) turning off the discharge path responsive solely to the single voltage applied directly to the gate electrode of the PFET, wherein turning on the PFET by the single voltage applied directly to the gate electrode of the PFET turns off the discharge path and permits the body to float and charge to accumulate on the body.

11. The method of claim 10, wherein step a) comprises electrically coupling the PFET body to a voltage source whenever the PFET gate electrode voltage is above a certain first voltage level.

12. An apparatus for reducing parasitic bipolar current in a field effect transistor (“

FET”

), comprising;

a first p-type FET (“

PFET”

) having a body disposed, at least in part, on an insulator; and

control circuitry coupled to the body and the gate of the first PFET, wherein the control circuitry comprises;

a body-charge control PFET, having first and second conducting electrodes and a gate electrode, wherein the body-charge control PFET first conducting electrode is electrically coupled to the body of the first PFET, and the body-charge control PFET second conducting electrode is electrically coupled to an electrical source; and

an inverter having an inverter input electrically coupled to the body-charge control PFET gate electrode, and an inverter output electrically coupled to the first PFET gate electrode, wherein the control circuitry controls charge on the first PFET solely responsive to a voltage applied directly to the body-charge control PFET gate, wherein the voltage applied to the body-charge control PFET gate electrode being above a certain first voltage level tends to turn off the body-charge control PFET and electrically isolate the body from the source, thereby permitting the body to float and a charge to accumulate on the body, and the voltage applied to the body-charge control PFET gate electrode being below a certain second voltage level tends to turn on the body-charge control PFET and electrically couple the body to the source, thereby discharging at least a portion of any charge accumulated on the body.

13. Control circuitry for reducing parasitic bipolar current in a first n-type field effect transistor (“

NFET”

), the first NFET having a body disposed, at least in part, on an insulator, the control circuitry consisting of;

a body-charge control NFET having first and second conducting electrodes and a gate electrode, wherein the body-charge control NFET first conducting electrode is electrically coupled to the body of the first NFET, and the body-charge control NFET second conducting electrode is electrically coupled to an electrical sink; and

an inverter having an inverter input electrically coupled to the first NFET gate electrode, and an inverter output electrically coupled to the body-charge control NFET gate electrode, so that a voltage applied to a gate electrode of the first NFET being above a certain first voltage level tends to turn on the first NFET and drive the inverter output voltage low, tending to turn off the body-charge control NFET, and the voltage applied to the first NFET gate electrode being below a certain second voltage level tends to turn off the first NFET, and drive the inverter output voltage high, tending to turn on the body-charge control NFET.

14. Control circuitry for reducing parasitic bipolar current in a first p-type, field effect transistor (“

PFET”

), the first PFET having a body disposed, at least in part, on an insulator, the control circuitry consisting of;

a body-charge control PFET having first and second conducting electrodes and a gate electrode, wherein the body-charge control PFET first conducting electrode is electrically coupled to the body of the first PFET, and the body-charge control PFET second conducting electrode is electrically coupled to an electrical source; and

an inverter having an inverter input electrically coupled to the body-charge control PFET gate electrode, and an inverter output electrically coupled to a gate electrode of the first PFET, so that a voltage applied to the body-charge control PFET gate electrode being above a certain first voltage level tends to turn off the body-charge control PFET and drive the inverter output voltage low, tending to turn on the first PFET, and the voltage applied to the body-charge control PFET gate electrode being below a certain second voltage level tends to turn on the body-charge control PFET and drive the inverter output voltage high, tending to turn off the first PFET.

15. Control circuitry for a complementary passgate device, the device having a first p-type, field effect transistor “

(PFET”

), the first PFET having a body disposed, at least in part, on an insulator, and a first n-type field effect transistor “

(NFET”

), the first NFET having a body disposed, at least in part, on an insulator, the control circuitry consisting of;

an inverter; and

a body-charge control NFET, having first and second conducting electrodes and a gate electrode, wherein the body-charge control NFET first conducting electrode is electrically coupled to the body of the first NFET, and the body-charge control NFET second conducting electrode is electrically coupled to an electrical sink, wherein an input of the inverter is electrically coupled to a gate electrode of the first NFET, and an output of the inverter is electrically coupled to the body-charge control NFET gate electrode and a gate electrode of the first PFET, so that a voltage applied to the first NFET gate electrode being above a certain first voltage level tends to turn on the first NFET, and drive the inverter output voltage low, tending to turn on the first PFET and turn off the body-charge control NFET, permitting the body of the first NFET to float and charge to accumulate on the body of the first NFET, and the voltage applied to the first NFET gate electrode being below a certain second voltage level tends to turn off the first NFET, and drive the inverter output voltage high, tending to turn off the first PFET and turn on the body-charge control NFET, discharging any charge accumulated on the body of the first NFET.

16. Control circuitry for a complementary passgate device, the device having a first p-type, field effect transistor “

(PFET”

), the first PFET having a body disposed, at least in part, on an insulator, and a first n-type field effect transistor “

(NFET”

), the first NFET having a body disposed, at least in part, on an insulator, the control circuitry consisting of;

an inverter;

a body-charge control NFET, having first and second conducting electrodes and a gate electrode, wherein the body-charge control NFET first conducting electrode is electrically coupled to the body of the first NFET, and the body-charge control NFET second conducting electrode is electrically coupled to an electrical sink,

a body-charge control PFET, having first and second conducting electrodes and a gate electrode, wherein the body-charge control PFET first conducting electrode is electrically coupled to the body of the first PFET, the body-charge control PFET second conducting electrode is electrically coupled to an electrical source, wherein an input of the inverter is coupled to a gate electrode of the first NFET and the body-charge control PFET gate electrode, and an output of the inverter is electrically coupled to the body-charge control NFET gate electrode and a gate electrode of the first PFET, so that a voltage applied to the first NFET gate electrode being above a certain first voltage level tends to i) turn on the first NFET and turn off the body-charge control PFET, permitting the body of the first PFET to float and charge to accumulate on the body of the first PFET, and ii) drive the inverter output voltage low, tending to turn on the first PFET and turn off the body-charge control NFET, permitting the body of the first NFET to float and charge to accumulate on the body of the first NFET, and the voltage applied to the first NFET gate electrode being below a certain second voltage level tends to i) turn off the first NFET and turn on the body-charge control PFET, discharging any charge accumulated on the body of the first PFET, and ii) drive the inverter output voltage high, tending to turn off the first PFET and turn on the body-charge control NFET, discharging any charge accumulated on the body of the first NFET.

17. A method for controlling a first n-type field effect transistor (“

NFET”

), the first NFET having a body disposed, at least in part, on an insulator, the method consisting of the steps of;

applying a first voltage level to a gate electrode of the first NFET, wherein the first voltage level tends to turn on the first NFET and drive an output voltage low for an inverter having an inverter input electrically coupled to the first NFET gate electrode and an inverter output electrically coupled to a gate electrode of a body-charge control NFET, wherein the body-charge control NFET has a first conducting electrode electrically coupled to the body of the first NFET, and a second conducting electrode electrically coupled to an electrical sink, so that the inverter output being low tends to turn off the body-charge control NFET; and

applying a second voltage level to the first NFET gate electrode, wherein the second voltage level tends to turn off the first NFET, and drive the inverter output voltage high, tending to turn on the body-charge control NFET.

18. A method for controlling a first p-type, field effect transistor (“

PFET”

), the first PFET having a body disposed, at least in part, on an insulator, the method consisting of the steps of;

applying a first voltage level to a gate electrode of a body-charge control PFET, wherein an inverter has an inverter input electrically coupled to the body-charge control PFET gate electrode, and an inverter output electrically coupled to a gate electrode of the first PFET, wherein the body-charge control PFET has a first conducting electrode electrically coupled to the body of the first PFET, and a second conducting electrode electrically coupled to an electrical source, and wherein the first voltage level tends to turn off the body-charge control PFET and drive the inverter output voltage low, tending to turn on the first PFET; and

applying a second voltage level to the body-charge control PFET gate electrode, wherein the second voltage level tends to turn on the body-charge control PFET and drive the inverter output voltage high, tending to turn off the first PFET.

19. A method for controlling a complementary passgate device, the device having a first p-type, field effect transistor “

(PFET”

), the first PFET having a body disposed, at least in part, on an insulator, and a first n-type field effect transistor “

(NFET”

), the first NFET having a body disposed, at least in part, on an insulator, the method consisting of the steps of;

applying a first voltage level to the first NFET gate electrode, wherein a body-charge control NFET has a first conducting electrode electrically coupled to the body of the first NFET, and a second conducting electrode electrically coupled to an electrical sink, and an input of an inverter is electrically coupled to a gate electrode of the first NFET, and an output of the inverter is electrically coupled to the body-charge control NFET gate electrode and a gate electrode of the first PFET, wherein the first voltage level tends to turn on the first NFET, and drive an inverter output voltage low, tending to turn on the first PFET and turn off the body-charge control NFET, permitting the body of the first NFET to float and charge to accumulate on the body of the first NFET;

applying a second voltage level to the first NFET gate electrode, wherein the second voltage level tends to turn off the first NFET, and drive the inverter output voltage high, tending to turn off the first PFET and turn on the body-charge control NFET, discharging any charge accumulated on the body of the first NFET.

20. A method for turning on and off a complementary passgate device, the device having a first p-type, field effect transistor “

(PFET”

), the first PFET having a body disposed, at least in part, on an insulator, and a first n-type field effect transistor “

(NFET”

), the first NFET having a body disposed, at least in part, on an insulator, the method consisting of the steps of;

applying a first voltage level to the first NFET gate electrode, wherein a body-charge control NFET has a first conducting electrode electrically coupled to the body of the first NFET, and a second conducting electrode electrically coupled to an electrical sink, wherein a body-charge control PFET has a first conducting electrode electrically coupled to the body of the first PFET, and a second conducting electrode electrically coupled to an electrical source, wherein an input of an inverter is electrically coupled to a gate electrode of the first NFET and the body-charge control PFET gate electrode, and an output of the inverter is electrically coupled to the body-charge control NFET gate electrode and the first PFET gate electrode, and wherein the first voltage level tends to i) turn on the first NFET and turn off the body-charge control PFET, permitting the body of the first PFET to float and charge to accumulate on the body of the first PFET, and ii) drive the inverter output voltage low, tending to turn on the first PFET and turn off the body-charge control NFET, permitting the body of the first NFET to float and charge to accumulate on the body of the first NFET; and

applying a second voltage level to a gate electrode of the first NFET gate electrode, wherein the second voltage level tends to i) turn off the first NFET and turn on the body-charge control PFET, discharging any charge accumulated on the body of the first PFET, and ii) drive the inverter output voltage high, tending to turn off the first PFET and turn on the body-charge control NFET, discharging any charge accumulated on the body of the first NFET.