Superscalar RISC instruction scheduling

  • US 6,289,433 B1
  • Filed: 06/10/1999
  • Issued: 09/11/2001
  • Est. Priority Date: 03/31/1992
  • Status: Expired due to Fees
First Claim
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1. A system for register renaming in a computer system capable of out-of-order instruction execution, comprising:

  • a temporary buffer comprising a plurality of storage locations for storing execution results, wherein an execution result for an instruction in an instruction window is stored at one of said plurality of storage locations, said one of said plurality of storage locations being assigned to said instruction in said instruction window; and

    tag assignment logic for receiving data dependency results from a data dependency checker and for outputting a tag comprising a temporary buffer storage location address in place of a register address for an operand of a first instruction, wherein said temporary buffer storage location address is an address of said operand in one of said plurality of storage locations if said first instruction is dependent on a previous one of said plurality of instructions in said instruction window for said operand.

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