Apparatus and method of implementing systems on silicon using dynamic-adaptive run-time reconfigurable circuits for processing multiple, independent data and control streams of varying rates

  • US 6,289,434 B1
  • Filed: 02/27/1998
  • Issued: 09/11/2001
  • Est. Priority Date: 02/28/1997
  • Status: Expired due to Term
First Claim
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1. An apparatus for processing data, comprising:

  • an addressable memory for storing the data, and a plurality of instructions, and having a plurality of input/outputs, each said input/output for providing and receiving at least one selected from the data and the instructions;

    a plurality of media processing units, each media processing unit having an input/output coupled to at least one of the addressable memory input/outputs and comprising;

    a multiplier having a data input coupled to the media processing unit input/output, an instruction input coupled to the media processing unit input/output, and a data output coupled to the media processing unit input/output;

    an arithmetic unit having a data input coupled to the media processing unit input/output, an instruction input coupled to the media processing unit input/output, and a data output coupled to the media processing unit input/output;

    an arithmetic logic unit having a data input coupled to the media processing unit input/output, an instruction input coupled to the media processing unit input/output, and a data output coupled to the media processing unit input/output, capable of operating concurrently with at least one selected from the multiplier and arithmetic unit; and

    a bit manipulation unit having a data input coupled to the media processing unit input/output, an instruction input coupled to the media processing unit input/output, and a data output coupled to the media processing unit input/output, capable of operating concurrently with the arithmetic logic unit and at least one selected from the multiplier and arithmetic unit;

    each of the plurality of media processors for performing at least one operation, simultaneously with the performance of other operations by other media processing units, each operation comprising;

    receiving at the media processor input/output an instruction from the memory;

    receiving at the media processor input/output data from the memory;

    processing the data responsive to the instruction received to produce at least one result; and

    providing at least one of the at least one result at the media processor input/output.

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