Semiconductor chip interconnect barrier material and fabrication method
First Claim
1. A microelectronic semiconductor interconnect structure formed on a substrate, the interconnect structure comprising:
- a trench feature fabricated in the substrate;
a barrier conformally deposited on the side walls and bottom of the trench, the barrier layer comprising TaxSnyNz; and
an overlying metallization layer deposited over the barrier layer within the trench.
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Accused Products
Abstract
A microelectronic semiconductor interconnect structure barrier and method of deposition provide improved conductive barrier material properties for high-performance device interconnects. The barrier comprises a dopant selected from the group consisting of platinum, palladium, iridium, rhodium, and tin. The barrier can comprise a refractory metal selected from the group consisting of tantalum, tungsten titanium, chromium, and cobalt, and can also comprise a third element selected from the group consisting of carbon, oxygen and nitrogen. The dopant and other barrier materials can be deposited by chemical-vapor deposition to achieve good step coverage and a relatively conformal thin film with a good nucleation surface for subsequent metallization such as copper metallization in one embodiment, the barrier suppresses diffusion of copper into other layers of the device, including the inter-metal dielectric, pre-metal dielectric, and transistor structures.
150 Citations
14 Claims
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1. A microelectronic semiconductor interconnect structure formed on a substrate, the interconnect structure comprising:
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a trench feature fabricated in the substrate;
a barrier conformally deposited on the side walls and bottom of the trench, the barrier layer comprising TaxSnyNz; and
an overlying metallization layer deposited over the barrier layer within the trench.
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2. A microelectronic semiconductor interconnect structure formed on a substrate, the interconnect structure comprising:
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a trench feature fabricated in the substrate;
a barrier conformally deposited on the side walls and bottom of the trench, the barrier layer comprising TixSnyNz; and
an overlying metallization layer deposited over the barrier layer within the trench.
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3. A microelectronic semiconductor interconnect structure formed on a substrate, the interconnect structure comprising:
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a trench feature fabricated in the substrate;
a barrier conformally deposited on the side walls and bottom of the trench, the barrier layer comprising WxSnyNz; and
an overlying metallization layer deposited over the barrier layer within the trench.
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4. A microelectronic semiconductor interconnect structure formed on a substrate, the interconnect structure comprising:
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a trench feature fabricated in the substrate;
a barrier conformally deposited on the side walls and bottom of the trench, the barrier layer comprising the elements [R][X1][X2][Y] wherein;
[R] is a refactory metal selected from the group consisting of Ta, W, Ti, Cr, and Co;
X1 is a first dopant selected from the group of Pt, Pd, Ir, Rh, and Sn;
X2 is a second dopant selected from the group of Pt, Pd, Ir, Rh, and Sn [Y] is an element selected from the group consisting of C, O, N; and
an overlying metallization layer deposited over the barrier layer within the trench. - View Dependent Claims (5, 6, 7)
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8. A microelectronic semiconductor interconnect structure formed on a substrate, the interconnect structure comprising:
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a barrier comprising the elements [R][X][Y] wherein;
[R] is a refractory metal of Ti;
[X] is a dopant of Sn; and
[Y] is an element of N.
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9. A microelectronic semiconductor interconnect structure formed on a substrate, the interconnect structure comprising:
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a barrier comprising the elements [R][X][Y] wherein;
[R] is a refractory metal of W;
[X] is a dopant of Sn; and
[Y] is an element of N.
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10. A microelectronic semiconductor interconnect structure formed on a substrate, the interconnect structure comprising:
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a barrier comprising the elements [R][X1][X2][Y] wherein;
[R] is a refractory metal of Ti;
[X1] is a first dopant selected from the group consisting of Pt, Pd, Ir, Rh, and Sn;
[X2] is a second dopant selected from the group consisting of Pt, Pd, Ir, Rh, and Sn; and
[Y] is an element of N. - View Dependent Claims (11, 12, 13, 14)
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Specification