Semiconductor chip interconnect barrier material and fabrication method

• US 6,294,836 B1
• Filed: 12/22/1998
• Issued: 09/25/2001
• Est. Priority Date: 12/22/1998
• Status: Expired due to Fees

• Current Assignee: CVC Products, Inc. (Veeco Instruments Incorporated)
• Original Assignee: CVC Products, Inc. (Veeco Instruments Incorporated)
• Inventors: Moslehi, Mehrdad M., Paranjpe, Ajit P., Bubber, Randhir S., Velo, Lino A.
• Primary Examiner(s): Loke, Steven
• Assistant Examiner(s): Owens, Douglas W.
• Application Number:
  US09/219,147
• Time in Patent Office: 1,008 Days
• Field of Search: 757/758, 757/761, 757/763, 757/767
• US Class Current: 257/767
• CPC Class Codes: H01L 21/2855 by physical means, e.g. sputtering, evaporation H01L21/28518 - H01L21/28537 and H01L21/28568 take precedence
• CPC Class Codes: H01L 21/28556 by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD H01L21/28518 - H01L21/28537 and H01L21/28568 take precedence
• CPC Class Codes: H01L 21/28568 the conductive layers comprising transition metals H01L21/28518 takes precedence
• CPC Class Codes: H01L 21/76843 formed in openings in a dielectric
• CPC Class Codes: H01L 21/76846 Layer combinations
• CPC Class Codes: H01L 21/76856 by treatment in plasmas or gaseous environments, e.g. nitriding a refractory metal liner
• CPC Class Codes: H01L 21/76876 for deposition from the gas phase, e.g. CVD
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 23/53238 Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 23/53295 Stacked insulating layers
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A microelectronic semiconductor interconnect structure barrier and method of deposition provide improved conductive barrier material properties for high-performance device interconnects. The barrier comprises a dopant selected from the group consisting of platinum, palladium, iridium, rhodium, and tin. The barrier can comprise a refractory metal selected from the group consisting of tantalum, tungsten titanium, chromium, and cobalt, and can also comprise a third element selected from the group consisting of carbon, oxygen and nitrogen. The dopant and other barrier materials can be deposited by chemical-vapor deposition to achieve good step coverage and a relatively conformal thin film with a good nucleation surface for subsequent metallization such as copper metallization in one embodiment, the barrier suppresses diffusion of copper into other layers of the device, including the inter-metal dielectric, pre-metal dielectric, and transistor structures.

Claims

1. A microelectronic semiconductor interconnect structure formed on a substrate, the interconnect structure comprising:

a trench feature fabricated in the substrate;

a barrier conformally deposited on the side walls and bottom of the trench, the barrier layer comprising Ta_xSn_yN_z; and

an overlying metallization layer deposited over the barrier layer within the trench.

2. A microelectronic semiconductor interconnect structure formed on a substrate, the interconnect structure comprising:

a trench feature fabricated in the substrate;

a barrier conformally deposited on the side walls and bottom of the trench, the barrier layer comprising Ti_xSn_yN_z; and

an overlying metallization layer deposited over the barrier layer within the trench.

3. A microelectronic semiconductor interconnect structure formed on a substrate, the interconnect structure comprising:

a trench feature fabricated in the substrate;

a barrier conformally deposited on the side walls and bottom of the trench, the barrier layer comprising W_xSn_yN_z; and

an overlying metallization layer deposited over the barrier layer within the trench.

4. A microelectronic semiconductor interconnect structure formed on a substrate, the interconnect structure comprising:

a trench feature fabricated in the substrate;

a barrier conformally deposited on the side walls and bottom of the trench, the barrier layer comprising the elements [R][X1][X2][Y] wherein;

[R] is a refactory metal selected from the group consisting of Ta, W, Ti, Cr, and Co;

X1 is a first dopant selected from the group of Pt, Pd, Ir, Rh, and Sn;

X2 is a second dopant selected from the group of Pt, Pd, Ir, Rh, and Sn

[Y] is an element selected from the group consisting of C, O, N; and

an overlying metallization layer deposited over the barrier layer within the trench.

5. The interconnect structure according to claim 4 wherein the barrier comprises Ti_xSn_yN_zPt_w.

6. The interconnect structure according to claim 4 wherein the barrier comprises Ta_xSn_yN_zPt_w.

7. The interconnect structure according to claim 4 wherein the barrier comprises W_xSn_yN_zPt_w.

8. A microelectronic semiconductor interconnect structure formed on a substrate, the interconnect structure comprising:

a barrier comprising the elements [R][X][Y] wherein;

[R] is a refractory metal of Ti;

[X] is a dopant of Sn; and

[Y] is an element of N.

9. A microelectronic semiconductor interconnect structure formed on a substrate, the interconnect structure comprising:

a barrier comprising the elements [R][X][Y] wherein;

[R] is a refractory metal of W;

[X] is a dopant of Sn; and

[Y] is an element of N.

10. A microelectronic semiconductor interconnect structure formed on a substrate, the interconnect structure comprising:

a barrier comprising the elements [R][X1][X2][Y] wherein;

[R] is a refractory metal of Ti;

[X1] is a first dopant selected from the group consisting of Pt, Pd, Ir, Rh, and Sn;

[X2] is a second dopant selected from the group consisting of Pt, Pd, Ir, Rh, and Sn; and

[Y] is an element of N.

11. The device according to claim 10 wherein the barrier comprises Ti_xSn_yN_zPt_w.

12. The device according to claim 10 wherein the barrier comprises Ta_xSn_yN_zPt_w.

13. The device according to claim 10 wherein the barrier comprises W_xSn_yN_zPt_w.

14. The device according to claim 10 wherein the interconnect structure further comprises a copper overlayer deposited on the barrier.