Low-voltage joystick port interface

• US 6,297,751 B1
• Filed: 07/10/1998
• Issued: 10/02/2001
• Est. Priority Date: 07/10/1998
• Status: Expired due to Fees

• Current Assignee: Fenner Investments Limited
• Original Assignee: Lucent Technologies, Inc. (Nokia Corporation)
• Inventors: Fadavi-Ardekani, Jalil, Niescier, Richard J., Livingston, Raymond S., Potts, David L.
• Primary Examiner(s): Horabik, Michael
• Assistant Examiner(s): WONG, ALBERT KANG
• Application Number:
  US09/113,503
• Time in Patent Office: 1,180 Days
• Field of Search: 341/20, 345/161, 345/212, 345/163, 710/18, 710/73, 710/2, 710/8, 710/37, 710/101, 327/333, 327/100, 327/142, 463/73
• US Class Current: 341/20
• CPC Class Codes: G06F 3/038 Control and interface arrangements therefor, e.g. drivers or device-embedded control circuitry

Abstract

The joystick port interface includes an integrated circuit receiving an analog joystick position measurement signal and outputting a digital pulse signal to a processor which signifies a joystick coordinate value. The integrated circuit includes a pulse generator and a bidirectional buffer circuit. The bidirectional buffer circuit receives the analog joystick position measurement signal and selectively discharges an RC network capacitor which provides this analog measurement. This implementation provides a joystick port which uses low-voltage CMOS VLSI structures which can interface a conventional high-voltage joystick with the processor.

Claims

1. An interface between a joystick device having a first source voltage and a processor, comprising:

a Resistor-Capacitor (RC) network, connected to the joystick device, said RC network having a capacitor that generates an analog joystick position measurement signal; and

an interface circuit having a second source voltage that is lower than the first source voltage, including

a buffer circuit, in a first operation mode of said interface, receiving said analog joystick position measurement signal, outputting a first logic state as a digital signal before said analog joystick measurement signal exceeds said predetermined threshold, and outputting a second logic state as said digital signal after said analog joystick measurement signal exceeds said predetermined threshold; and

a pulse generator generating a pulse based on said digital signal in said first operation mode of said interface, a width of said pulse representing a coordinate position of said joystick device, the capacitance value of said capacitor being a function of said predetermined threshold that prevents deviation of the width of said pulse from expected values.

2. The interface of claim 1, wherein said pulse generator enters a disabled state in response to a control signal from said processor, and said pulse generator does not generate said pulse in said disabled state and does not dissipate power in said disabled state.

3. The interface of claim 1, wherein said buffer circuit is connected to a charge storage device, and places said charge storage device in a discharged state in a second operation mode of said interface.

4. The interface of claim 3, wherein said buffer circuit permits said charge storage device to begin charging in said first operation mode of said interface.

5. The interface of claim 3, wherein said pulse generator enters a disabled state in response to a control signal from said processor in said second operation mode of said interface, and said pulse generator does not generate said pulse in said disabled state.

6. The interface of claim 1, wherein said pulse generator is a latch.

7. The interface of claim 6, wherein said latch is cleared at a beginning of said first operation mode of said interface by a control signal from said processor, and said latch stores a logic “

1”

when said digital signal is said second logic state.

8. The interface of claim 1, wherein said RC network capacitor is preselected as a function of said predetermined threshold to satisfy the formula:

$\mathrm{Cnew}=\frac{11<br><br>\text{\hspace{1em}<br><br>}<br><br>n<br><br>\text{\hspace{1em}<br><br>}<br><br>F}{\ln <br><br>\left(\frac{5<br><br>V}{5<br><br>V-\mathrm{Vtnew}}\right)}<br><br>\text{\hspace{1em}<br><br>}<br><br>\mathrm{for}<br><br>\text{\hspace{1em}<br><br>}<br><br>\mathrm{Vtnew}<<br><br>5.0<br><br>\text{\hspace{1em}<br><br>}<br><br>\mathrm{Volts},$

where Cnew represents the capacitance of the RC network capacitor, and Vtnew represents said predetermined threshold.

9. A processor based system, comprising:

a processor;

a joystick device having a first source voltage; and

an interface interfacing said joystick device with said processor, said interface including,

a Resistor-Capacitor (RC) network, connected to the joystick device, said RC network having a capacitor that generates an analog joystick position measurement signal; and

an interface circuit having a second source voltage that is lower than the first source voltage, including

a buffer circuit, in a first operation mode of said interface, receiving said analog joystick position measurement signal, outputting a first logic state as a digital signal before said analog joystick measurement signal exceeds said predetermined threshold, and outputting a second logic state as said digital signal after said analog joystick measurement signal exceeds said predetermined threshold, and

a pulse generator generating a pulse based on said digital signal in said first operation mode of said interface, a width of said pulse representing a coordinate position of said joystick device, and outputting said pulse to said processor, wherein the capacitance value of said capacitor is a function of said predetermined threshold that prevents deviation of the width of said pulse from expected values.

10. The processor based system of claim 9, wherein said pulse generator enters a disabled state in response to a control signal from said processor, and said pulse generator does not generate said pulse in said disabled state and does not dissipate power in said disabled state.

11. The processor based system of claim 9, wherein said buffer circuit is connected to a charge storage device, places said charge storage device in a discharged state in a second operation mode of said interface, and permits said charge storage device to begin charging in said first operation mode of said interface.

12. The processor based system of claim 9, wherein said pulse generator is a latch, said latch is cleared at a beginning of said first operation mode of said interface by a control signal from said processor, said interface by a control signal from said processor, and said latch stores a logic “

1”

when said digital signal is said second logic state.

13. The interface of claim 9, wherein said RC network capacitor is preselected as a function of said predetermined threshold to satisfy the formula:

$\mathrm{Cnew}=\frac{11<br><br>\text{\hspace{1em}<br><br>}<br><br>n<br><br>\text{\hspace{1em}<br><br>}<br><br>F}{\ln <br><br>\left(\frac{5<br><br>V}{5<br><br>V-\mathrm{Vtnew}}\right)}<br><br>\text{\hspace{1em}<br><br>}<br><br>\mathrm{for}<br><br>\text{\hspace{1em}<br><br>}<br><br>\mathrm{Vtnew}<<br><br>5.0<br><br>\text{\hspace{1em}<br><br>}<br><br>\mathrm{Volts},$

where Cnew represents the capacitance of the RC network capacitor, and Vtnew represents said predetermined threshold.

14. A method of interfacing a joystick device having a first source voltage with a processor, comprising:

(a) receiving an analog joystick measurement signal from a Resistor-Capacitor (RC) network connected to the joystick device, said RC network having a capacitor that generates said analog joystick measurement signal;

(b) generating a digital signal, the logic level of said digital signal being set based on whether said analog joystick measurement signal exceeds a predetermined threshold level, said digital signal being generated by an interface circuit having a second source voltage that is lower than the first source voltage;

(c) outputting said digital signal to a pulse generator;

(d) generating a pulse based on the logic level of said first digital signal, a width of said pulse representing a coordinate position of said joystick device; and

(e) outputting said pulse to said processor,

wherein the capacitance value of said capacitor is a function of said predetermined threshold level that prevents deviation of the width of said pulse from expected values.

15. The method of claim 14, wherein

said steps (a)-(e) are performed in a first mode of operation;

and further including,

(f) placing said capacitor in a discharged state in a second mode of operation.

16. The method of claim 15, further comprising:

(g) permitting said charge storage device to begin charging in said first mode of operation.

17. The method of claim 15, further comprising:

(g) prohibiting said steps (d) and (e) in response to a control signal from said processor in said second mode of operation.

18. The method of claim 14, further comprising:

(f) prohibiting said steps (d) and (e) in response to a control signal from said processor.

19. The method of claim 14, wherein the capacitance value of said capacitor satisfies the formula:

$\mathrm{Cnew}=\frac{11<br><br>\text{\hspace{1em}<br><br>}<br><br>n<br><br>\text{\hspace{1em}<br><br>}<br><br>F}{\ln <br><br>\left(\frac{5<br><br>V}{5<br><br>V-\mathrm{Vtnew}}\right)}<br><br>\text{\hspace{1em}<br><br>}<br><br>\mathrm{for}<br><br>\text{\hspace{1em}<br><br>}<br><br>\mathrm{Vtnew}<<br><br>5.0<br><br>\text{\hspace{1em}<br><br>}<br><br>\mathrm{Volts},$

where Cnew represents the capacitance of the RC network capacitor, and Vtnew represents said predetermined threshold level.