High voltage PMOS level shifter

• US 6,300,796 B1
• Filed: 02/19/1999
• Issued: 10/09/2001
• Est. Priority Date: 02/19/1999
• Status: Expired due to Term

• Current Assignee: IXYS Intl Limited (Littelfuse Incorporated)
• Original Assignee: ZiLOG Incorporated (Littelfuse Incorporated)
• Inventors: Troutman, Bruce Lee, Manos, II, Peter D.
• Primary Examiner(s): Tokar, Michael
• Assistant Examiner(s): TRAN, ANH Q
• Application Number:
  US09/253,432
• Time in Patent Office: 963 Days
• Field of Search: 326/81, 326/83, 326/68, 326/120, 326/122, 326/119, 326/121
• US Class Current: 326/81
• CPC Class Codes: H03K 17/102 in field-effect transistor switches
• CPC Class Codes: H03K 3/356113 using additional transistors in the input circuit

Abstract

A high voltage level shifter includes one or more complementary pairs of transistors connected together in series separate the output terminal from the input terminal so as to prevent junction breakdowns, oxide breakdowns, and punch-through breakdowns.

Claims

1. A high voltage level shifter for receiving an input voltage signal having a predetermined magnitude of voltage and for generating an output voltage signal having a different magnitude of voltage, comprising:

a first pair of first and second field effect transistors of a first conductivity type connecting together in series between a voltage source line and a first node and having respective gate electrodes connected to a second node and respective substrates connected to said voltage source line;

a second pair of third and fourth field effect transistors of said first conductivity type connecting together in series between said voltage source line and said second node and having respective gate electrodes connected to said first node and respective substrates connected to said voltage source line;

a fifth field effect transistor of a second conductivity type connecting between said first node and a voltage reference line and having a gate electrode connected to an input terminal and a substrate connected to said voltage reference line;

an inverter having an input connected to said input terminal and an output;

a sixth field effect transistor of said second conductivity type connecting between said second node and said voltage reference line and having a gate electrode connected to said output of said inverter and a substrate connected to said voltage reference line;

an output terminal;

a third pair of seventh and eighth field effect transistors of said first conductivity type connecting together in series between said voltage source line and said output terminal and having respective gate electrodes connected to said first node and respective substrates connected to said voltage source line; and

a ninth field effect transistor of said second conductivity type connecting between said output terminal and said voltage reference line and having a gate electrode connected to said first node and a substrate connected to said voltage reference line.

3. The high voltage level shifter according to claim 1, in which said voltage source line is approximately between 16 and 20 volts and said voltage reference line is approximately 0 volt.

4. The high voltage level shifter of claim 3, wherein said input voltage signal is approximately 0 volt and said output voltage signal is approximately 0 volt.

5. The high voltage level shifter of claim 3, wherein said input voltage signal is approximately between 2 and 5 volts and said output voltage signal is approximately between 16 and 20 volts.

10. The high voltage level shifter according to claim 1 or 2, in which said seventh transistor is a depletion PMOS transistor, wherein said eighth transistor is an enhancement PMOS transistor, and wherein said ninth transistor is an intrinsic NMOS transistor.

13. The high voltage level shifter according to claim 10, in which said substrates of said PMOS transistors of each said pair share a common N-well.

14. The high voltage level shifter according to claim 10, wherein said enhancement PMOS transistors have a breakdown characteristic of less than approximately 17 volts and wherein said depletion PMOS transistors have a breakdown characteristic of greater than approximately 17 volts.

2. A high voltage level shifter for receiving an input voltage signal having a predetermined magnitude of voltage and for generating an output voltage signal having a different magnitude of voltage, comprising:

a first pair of first and second field effect transistors of a first conductivity type connecting together in series between a voltage source line and a first node and having respective gate electrodes connected to a second node and respective substrates connected to said voltage source line;

a second pair of third and fourth field effect transistors of said first conductivity type connecting together in series between said voltage source line and said second node and having respective gate electrodes connected to said first node and respective substrates connected to said voltage source line;

a fifth field effect transistor of a second conductivity type connecting between said first node and a voltage reference line and having a gate electrode connected to an input terminal and a substrate connected to said voltage reference line;

an inverter having an input connected to said input terminal and an output;

a sixth field effect transistor of said second conductivity type connecting between said second node and said voltage reference line and having a gate electrode connected to said output of said inverter and a substrate connected to said voltage reference line;

an output terminal;

a third pair of seventh and eighth field effect transistors of said first conductivity type connecting together in series between said voltage source line and said output terminal and having respective gate electrodes connected to said second node and respective substrates connected to said voltage source line; and

a ninth field effect transistor of said second conductivity type connecting between said output terminal and said voltage reference line and having a gate electrode connected to said second node and a substrate connected to said voltage reference line.

6. The high voltage level shifter according to claim 2, in which said voltage source line is approximately between 16 and 20 volts and said voltage reference line is approximately 0 volt.

7. The high voltage level shifter of claim 6, wherein said input voltage signal is 0 volt and said output voltage signal is approximately between 16 and 20 volts.

8. The high voltage level shifter of claim 6, wherein said input voltage signal is approximately between 2 to 5 volts and said output voltage signal is 0 volt.

9. A high voltage level shifter for receiving an input voltage signal having a predetermined magnitude of voltage and for generating an output voltage signal having a different magnitude of voltage, comprising:

a first pair of first and second field effect transistors of a first conductivity type connecting together in series between a voltage source line and a first node and having respective gate electrodes connected to a second node and respective substrates connected to said voltage source line;

a second pair of third and fourth field effect transistors of said first conductivity type connecting together in series between said voltage source line and said second node and having respective gate electrodes connected to said first node and respective substrates connected to said voltage source line;

a fifth field effect transistor of a second conductivity type connecting between said first node and a voltage reference line and having a gate electrode connected to an input terminal and a substrate connected to said voltage reference line;

an inverter having an input connected to said input terminal and an output;

a sixth field effect transistor of said second conductivity type connecting between said second node and said voltage reference line and having a gate electrode connected to said output of said inverter and a substrate connected to said voltage reference line; and

an output terminal, wherein said first and third transistors are depletion PMOS transistors, wherein said second and fourth transistors are enhancement PMOS transistors, and wherein said fifth and sixth transistors are intrinsic NMOS transistors.

11. The high voltage level shifter of claim 9, wherein said output terminal is connected to said first node.

12. The high voltage level shifter of claim 9, wherein said output terminal is connected to said first node.

15. The high voltage level shifter of claim 9, wherein said inverter is a low voltage inverter.

36. The high voltage level shifter according to claim 12, in which said voltage source line is approximately between 16 and 20 volts and said voltage reference line is approximately 0 volt.

37. The high voltage level shifter of claim 36, wherein said input voltage signal is approximately 0 volt and said output voltage signal is approximately 0 volt.

38. The high voltage level shifter of claim 36, wherein said input voltage signal is approximately between 2 and 5 volts and said output voltage signal is approximately between 16 and 20 volts.

39. The high voltage level shifter according to claim 12 or 2, in which said voltage source line is approximately between 16 and 20 volts and said voltage reference line is approximately 0 volt.

40. The high voltage level shifter of claim 39, wherein said input voltage signal is 0 volt and said output voltage is approximately between 16 and 20 volts.

41. The high voltage level shifter of claim 39, wherein said input voltage signal is approximately between 2 to 5 volts and said output voltage signal is 0 volt.

42. The high voltage level shifter according to claim 9, in which said substrates of said PMOS transistors of each said pair share a common N-well.

43. The high voltage level shifter according to claim 9, wherein said enhancement PMOS transistors have a breakdown characteristic of less than approximately 17 volts and wherein said depletion PMOS transistors have a breakdown characteristic of greater than approximately 17 volts.

16. A high voltage PMOS level shifter for receiving an input voltage signal having a predetermined magnitude of voltage and for generating an output voltage signal having a different magnitude of voltage, comprising:

at least two pairs of transistors for high voltage level shifting in response to said input voltage signal, wherein each of said at least two pairs has an enhancement PMOS transistor and a depletion PMOS transistor that are connected together in series; and

at least two transistors and at least one inverter for providing said input voltage signal to gates of said at least two pairs of transistors.

17. The high voltage PMOS level shifter of claim 16, wherein said at least one inverter is a low voltage inverter.

18. The high voltage PMOS level shifter of claim 16, wherein a first pair of the at least two pairs is connected between a first voltage source and a first node, further wherein gate electrodes of said transistors of said first pair are connected to a second node and wherein substrates of said transistors of said first pair are connected to said first voltage source.

19. The high voltage PMOS level shifter of claim 18, wherein a second pair of the at least two pairs is connected between said first voltage source and a second node, further wherein gate electrodes of said transistors of said second pair are connected to said first node and wherein substrates of said transistors of said second pair are connected to said first voltage source.

20. The high voltage PMOS level shifter of claim 19, wherein a first transistor of said at least two transistors is connected between said first node and a second voltage source, includes a gate electrode connected to an input terminal for inputting said input voltage signal, and includes a substrate connected to said second voltage source.

21. The high voltage PMOS level shifter of claim 20, wherein said at least one inverter has an input connected to said input terminal and an output.

22. The high voltage PMOS level shifter of claim 21, wherein a second transistor of said at least two transistors is connected between said second node and a second voltage source, includes a gate electrode connected to said output of said first transistor, and includes a substrate connected to said second voltage source.

23. The high voltage PMOS level shifter of claim 22, wherein said first voltage source is approximately between 16 and 20 volts and wherein the second voltage source is approximately 0 volt.

24. The high voltage PMOS level shifter of claim 23, wherein said second node is connected to an output terminal for outputting said output voltage signal.

25. The high voltage PMOS level shifter of claim 23, wherein said first node is connected to an output terminal for outputting said output voltage signal.

26. The high voltage PMOS level shifter of claim 24, wherein said output voltage signal is approximately between 16 and 20 volts when said input voltage signal is approximately 0 volt and wherein said output voltage signal is approximately 0 volt when input voltage signal is approximately between 2 and 5 volts.

27. The high voltage PMOS level shifter of claim 25, wherein said output voltage signal is approximately between 16 and 20 volts when said input voltage signal is approximately between 2 and 5 volts and wherein said output voltage signal is approximately 0 volt when input voltage signal is approximately 0 volt.

28. The high voltage PMOS level shifter of claim 16, wherein said at least two transistors are intrinsic NMOS devices.

29. The high voltage PMOS level shifter of claim 16, wherein said substrates of said transistors of each said at least two pairs share a common N-well.

30. The high voltage PMOS level shifter of claim 16, wherein said enhancement PMOS transistor has a breakdown characteristic of less than approximately 17 volts and wherein said depletion PMOS transistor has a breakdown characteristic of greater than approximately 17 volts.

31. A circuit comprising:

a constant first voltage source approximately 16 and 20 volts,

a second voltage source varying approximately between 0 volt and approximately 16 and 20 volts,

a third voltage source varying approximately between 0 volt and approximately 16 and 20 volts when said second voltage source is approximately 16 and 20 volts and when said second voltage source is approximately 0 volt respectively,

an enhancement PMOS transistor having a breakdown characteristic of less than approximately 17 volts; and

a depletion PMOS transistor having a breakdown characteristic of greater than approximately 17 volts, wherein said enhancement PMOS transistor and said depletion PMOS transistor are connected together in series and in between said first voltage source and said third voltage source and include respective substrates connected to said first voltage source.

32. The circuit of claim 31, wherein said transistors turn on to conduct when said second voltage source is approximately 0 volt and thereby third voltage source is approximately 16 and 20 volts.

33. The circuit of claim 31, wherein said transistors are off when second voltage source is approximately 16 and 20 volts and thereby third voltage source is approximately 0 volt.

34. The circuit of claim 31, wherein said substrates of said enhancement PMOS transistor and said depletion PMOS transistor share a common N-well.

35. A method of protecting an enhancement PMOS transistor from high voltage breakdowns, which comprises:

applying a first voltage selectively approximately 0 volt or approximately between 16 and 20 volts to gate electrodes of an enhancement PMOS transistor and a depletion PMOS transistor and thereby turning on both said transistors to conduct and turning off both said transistors respectively, wherein said transistors are connected together in series and in between a second voltage and a third voltage,

applying said second constant voltage approximately between 16 and 20 volts, to substrates of said enhancement PMOS transistor and said depletion PMOS transistor when both said transistors are on and off and to a source of said enhancement PMOS transistor when said enhancement PMOS transistor is on and off, and

applying said third voltage selectively approximately 0 volt and approximately between 16 and 20 volts when said transistors are off and on respectively, to a drain of said depletion PMOS transistor.