Voltage regulated charge pump

• US 6,300,820 B1
• Filed: 02/07/2000
• Issued: 10/09/2001
• Est. Priority Date: 02/07/2000
• Status: Expired due to Fees

• Current Assignee: Exar Corporation (Maxlinear Incorporated)
• Original Assignee: Exar Corporation (Maxlinear Incorporated)
• Inventors: Gregorian, Roubik, Fotouhi, Bahram
• Primary Examiner(s): ZWEIZIG, JEFFERY SHAWN
• Application Number:
  US09/498,699
• Time in Patent Office: 610 Days
• Field of Search: 327/530, 327/534, 327/535, 327/536, 327/540, 327/541
• US Class Current: 327/536
• CPC Class Codes: H02M 3/07 using capacitors charged and discharged alternately by semiconductor devices with control electrode , e.g. charge pumps

Abstract

A voltage regulated charge pump is disclosed which is capable of regulating its output voltage without radiating switching noise or consuming more power than is necessary to maintain the output at its targeted level. The voltage regulated charge pump circuit and its method of regulation, according to the present invention, can reliably drive transmission lines in networking system and communication applications.

Claims

1. A regulated on-chip voltage generator comprising:

a charge pump circuit coupled between a voltage source and an intermediate node having an intermediate voltage, and configured to generate an output voltage at an output node, the charge pump circuit having a first transistor switch coupled between the intermediate node and a first terminal of a capacitor and a second transistor switch coupled between a second terminal of the capacitor and the output node; and

a voltage regulator circuit having a first input coupled to the output voltage, a second input coupled to a reference voltage generator, and an output coupled to the intermediate voltage,

wherein, the voltage regulator circuit is configured to modulate the intermediate voltage for regulating the output voltage within the charge pump circuit.

2. The generator of claim 1, the charge pump circuit further comprising:

a third transistor switch coupled between the first terminal of the capacitor and the voltage source; and

a fourth transistor switch coupled between and the second terminal of the capacitor and the voltage source.

3. The regulated on-chip voltage generator of claim 1, wherein the voltage regulator circuit comprises:

a voltage translation circuit configured to receive the output voltage and to output a fraction thereof;

a reference voltage configured to provide a reference voltage; and

an error amplifier having a first amplifier input coupled to the voltage translation circuit to receive the fraction of output voltage, a second amplifier input coupled to the reference voltage generator, and an amplifier output configured to modulate the intermediate voltage.

4. The regulated on-chip voltage generator of claim 3, further comprising:

a buffer circuit coupled to the amplifier output and configured to modulate the intermediate voltage.

5. The regulated on-chip voltage generator of claim 3, wherein the voltage translator comprises:

a voltage dividing network configured to provide a fraction of the output voltage.

6. The regulated on-chip voltage generator of claim 5, wherein the voltage dividing network further comprises:

a voltage divider node;

a first resistance element coupled between the output voltage and the voltage divider node; and

a second resistance element coupled between the voltage divider node and a bias voltage.

7. The regulated on-chip voltage generator of claim 6, wherein the bias voltage is electrical ground.

8. The regulated on-chip voltage generator of claim 3, wherein the voltage reference generator is a band-gap voltage reference.

9. The regulated on-chip voltage generator of claim 3, wherein the error amplifier is an operational amplifier.

10. The regulated on-chip voltage generator of claim 9, wherein the operational amplifier is non-inverting.

11. The regulated on-chip voltage generator of claim 4, wherein the buffer comprises a bipolar transistor having an emitter terminal coupled to the intermediate voltage, a base terminal coupled to the amplifier output and a collector terminal coupled to a supply voltage.

12. The regulated on-chip voltage generator of claim 11, wherein the bipolar transistor is a PNP device configured as a emitter-follower.

13. The regulated on-chip voltage generator of claim 11, wherein the supply voltage is at electrical ground.

14. The regulated on-chip voltage generator of claim 11, wherein the supply voltage is a negative voltage source.

15. The regulated on-chip voltage generator of claim 4, wherein the buffer comprises two or more bipolar transistors configured to operate as a Darlington transistor.

16. The regulated on-chip voltage generator of claim 14, wherein the two or more bipolar transistors are PNP devices.

17. The regulated on-chip voltage generator of claim 15, the Darlington transistor comprising a first transistor having a first base, a first emitter, and a first collector, and a second transistor having a second base, a second emitter, and a second collector, wherein

the first base is coupled to the amplifier output;

the first collector is coupled to both the second collector and the supply voltage;

the first emitter is coupled to the second base; and

the second emitter is coupled to the intermediate voltage.

18. A voltage regulated charge pump fabricated on a semiconductor substrate, comprising:

a charge pump circuit having an output and an intermediate voltage level at an intermediate node;

a voltage translator circuit configured to receive and to translate an output voltage from the charge pump output into a fraction thereof;

a reference voltage generator for providing a constant reference voltage, where the constant reference voltage remains substantially constant over each phase of the charge pump;

an error amplifier configured to compare the fraction of the output voltage to the reference voltage, the amplifier having a first input coupled to receive the fraction of the output voltage and a second input coupled to receive the constant reference voltage, and an output; and

a buffer circuit coupled between the error amplifier output and the intermediate node,

wherein a voltage at the intermediate node is modulated in response to an output of the buffer circuit to regulate the output voltage of the charge pump.

19. A method for regulating an output voltage from a charge pump fabricated on a semiconductor substrate, comprising the steps of:

generating the output voltage according to the method of;

transferring charge from a supply voltage source through a first transistor to a first terminal of a capacitor; and

transferring charge from a second terminal of the capacitor through a second transistor to an intermediate voltage node having an intermediate voltage;

receiving the output voltage from the charge pump;

generating a fraction of the output voltage;

sampling the fraction of the output voltage;

detecting a deviation of the fraction of the output voltage from a reference voltage, and generating an error signal;

modulating a signal on the intermediate voltage node in response to the error signal; and

feeding back the modulated signal to the charge pump, wherein the modulated signal is used by the charge pump to regulate the output voltage of the charge pump.

20. The method of claim 19, further comprising:

transferring charge from the supply voltage source through a third transistor during a next period of time to the second terminal of the capacitor; and

transferring charge from the first terminal of the capacitor through a fourth transistor during the next period of time to provide the output voltage.

21. The method of claim 19, wherein the step of generating a fraction of the output voltage further comprises the step of dividing the output voltage within a voltage divider circuit.

22. The method of claim 19, wherein the step of generating a fraction of the output voltage further comprises the step of dividing the output voltage within a voltage divider circuit.